VHDL参考例程

说明：  AD9361资料文档及其寄存器配置参数文档(Ad9361 data and configuration parameter document)

说明：  Xilinx Vivado 2018 License File

早迟门（early late gate），比特同步算法，该文档详细的说明了早迟门算法的原理以及具体的实现步骤(Early late gate (early late gate), bit synchronization algorithm, the document explains in detail the principles of early-late gate method and the specific implementation steps)

检测上升沿的verilog程序，有验证程序，可用synplify验证-Detection of rising edge of the Verilog procedures, there is the verification process can be used to verify Synplify

用窗函数法设计一个线性相位FIR数字低通滤波器，用理想低通滤波器作为逼近滤波器，通带截止频率为0.2 ，阻带截止频率为0.4 ，阻带衰减不小于-40dB。(Window function method to design a linear phase FIR digital low-pass filter, as an ideal low-pass filter for approximation filter passband cutoff frequency of 0.2 stopband cutoff frequency of 0.4, the stop-band attenuation of less than-40dB.)

说明：  在zedboard上运行的神经网络架构，方便移植。(Run lenet-5 on zedboard)

说明：  RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

LBM用于Poiseuille流初学者程序，直接反弹格式(LBM Poiseuille)

黑金刚FPGA开发板使用说明文档，讲诉了NIOS和Qsys的详细开发步奏，值得学习。(KINGBOX FPGA development board documentation, recounts in detail the development of step-outs and Qsys NIOS, it is worth learning.)

实现beep发出1234567的音乐声音-beep 123456