d ,t flip flop

ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder

说明：  能实现输入0.5 1 5块钱的累加，然后对应购买的商品价格进行比较，显示找的钱数或错误灯(MY English is very good)

说明：  频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)

这是关于赢vhdl语言变得信号采集卡，很有实用性，大家可以来看看的。-This is about winning VHDL language has become signal acquisition card, is very practical, we can take a look at the.

该程序描述了运用FPGA进行控制的S形曲线和其他传统加减速控制曲线方法的控制曲线比较研究。(This program is compiled in matlab circumstance。Describing the approach of S-curve control method in FPGA in machine controlling.)

设计一简易数字频率计，其基本要求是： 1)测量频率范围0～999999Hz； 2)最大读数999999HZ,闸门信号的采样时间为1s；. 3)被测信号可以是正弦波、三角波和方波； 4)显示方式为6位十进制数显示； 5）具有超过量程报警功能。 5)输入信号最大幅值可扩展。 6）测量误差小于+-0.1%。 7)完成全部设计后，可使用EWB进行仿真，检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are: 1) The measuring frequency range is 0-999999 Hz. 2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s. 3) The measured signal can be sine wave, triangle wave and square wave. 4) The display mode is 6-bit decimal number display. 5) It has alarm function beyond range. 5) The maximum amplitude of input signal can be expanded. 6) The measurement error is less than +0.1%. 7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)

基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来(Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it)

Verilog版的C51核(DW8051)-Verilog version of the C51 core (DW8051)

4：2优先编码设计中的VHDL来为每个输入分配优先级。在CMOS布局1复用器：还设计了4个

verilog program for 8-bit multiplier