procedures in the report, with QuartusII operations, the attention to word from...

这是用Verilog HDL写的可调占空比分频控制器，可以挂在Avalon总线上使用-This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use

verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。(verilog halfband FIR)

说明：  关于quartus与modelsim 仿真(about quartus and modelsim simulator)

基于Verilog HDL的通信系统设计(Design of communication system based on Verilog HDL)

Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.

十分基础的CCD的测试程序，大家可以下载调试CCD(this is a ccd test chengxu ,it is very good to use ,you can down it )

使用FPGA完成AGC 自动增益的代码，适合初学者(FPGA to complete the use of AGC automatic gain code, suitable for beginners)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)

通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)

基于有限状态机的健壮性测试研究。 关键词：健壮性测试；增强有限状态机；全球平台；安全通道协议(The Research of Robustness Testing Based on FSM)