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COSTAS_LOOP
用verilog编写的科斯塔斯环,希望有帮助(Costas loop written in verilog helpful)
- 2012-10-31 23:01:23下载
- 积分:1
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FDPIM_Encode
关于语音通信信道调制的程序代码,是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)
- 2013-12-11 09:27:39下载
- 积分:1
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plldesign
pll(phase locked loop) is used to fix the circuit to particular frequency
- 2014-03-18 17:14:26下载
- 积分:1
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中科院VHDL学习资料,很好的东西,希望对大家有用
中科院VHDL学习资料,很好的东西,希望对大家有用-Chinese Academy of Sciences VHDL learning materials, a very good thing, everyone would like to be useful
- 2022-09-02 02:55:03下载
- 积分:1
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lisa-vhdl2va
通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)
- 2013-12-12 11:17:18下载
- 积分:1
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hdb3_VHDL
hdb3 using language VHDL(Indoor using VHDL language)
- 2020-12-01 20:19:27下载
- 积分:1
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A complete signal test procedures, the various indicators of signal integrity te...
一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析-A complete signal test procedures, the various indicators of signal integrity testing, and analysis of
- 2022-03-23 02:41:40下载
- 积分:1
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Verilog-learning-experience
初学学习verilog的经验,可以帮助新手以正确的思维方式,学习方法学习。(Verilog learning experience)
- 2013-09-30 09:51:04下载
- 积分:1
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该程序实现的是n位全加器,首先用与非门实现一位全家器,最后实现n位的全加器。...
该程序实现的是n位全加器,首先用与非门实现一位全家器,最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.
- 2022-01-24 17:35:43下载
- 积分:1
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FPGA-Labview
Design FPGA in Labview
- 2015-05-27 23:39:27下载
- 积分:1