-
用verilog写的基于cpld的出租车计费器的源码,需要的参考一下
用verilog写的基于cpld的出租车计费器的源码,需要的参考一下-Use verilog to write a taxi based cpld billing device source code, need to refer to
- 2022-06-11 23:05:49下载
- 积分:1
-
PCI_arbi
PCI arbi verilog source code
- 2009-03-29 18:04:41下载
- 积分:1
-
DE2_115_pin_assignments
de2-115引脚的配置,quartusII的设置(de2-115 configuration pins, quartusII settings)
- 2020-07-01 13:40:02下载
- 积分:1
-
通过VHDL语言的例子,对FPGA的VHDL语言的原型(第七章)是
应用背景FPGA原型的VHDL例子提供一系列清晰,易于遵循的快速代码开发模板;大量的实际例子来说明和强化的概念和设计技术;现实可实施的项目和测试在Xilinx原型板;深入探索和Xilinx PicoBlaze软核微处理器。关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。
- 2022-08-13 16:44:37下载
- 积分:1
-
其基于FIFO的设计
its a Fifo BASED design
i also Interface DAC2904
- 2023-02-01 15:35:04下载
- 积分:1
-
alu
说明: 用Verilog编写的简单的运算单元(ALU),可实现加、减、与、或、异或、非、左、右移等功能(Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right)
- 2009-07-28 16:20:52下载
- 积分:1
-
DA
说明: DOCUMENT ON DISTRIBUTED ARITHMATIC
- 2014-02-05 17:06:51下载
- 积分:1
-
sha1_v01
说明: SHA-1加密算法的IP核,内涵文档,仿真测试文件(SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file)
- 2008-10-15 09:05:58下载
- 积分:1
-
CSC_mat
彩色空间转换,RGB和YUV互转的matlab源码(RGB converting to YUV, YUV converting to RGB, Matlab source code)
- 2014-12-24 10:15:57下载
- 积分:1
-
hssdrc IP核的可配置的通用SDRAM控制器的自适应银行…
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
- 2022-09-20 22:10:03下载
- 积分:1