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BLDC_Simplorer_Maxwell_Cosimulation
这个是永磁无刷直流电机的本体结构和控制电路的联合仿真,既可以设计电机的结构,又可以搭电机的控制系统。(This is the body structure of the permanent magnet brushless DC motor and control circuit co-simulation, both the structure of the motor can be designed, they can take control of the motor system.)
- 2021-03-26 11:39:13下载
- 积分:1
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FDPIM_Encode
关于语音通信信道调制的程序代码,是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)
- 2013-12-11 09:27:39下载
- 积分:1
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以太网总线源代码,里面有详细的文档说明,已经过FPGA验证。...
以太网总线源代码,里面有详细的文档说明,已经过FPGA验证。-Ethernet bus source code, which has a detailed document that has been FPGA verification.
- 2023-08-25 00:30:05下载
- 积分:1
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serial_communication
说明: 串口操作源代码,本代码采用veilog hdl语言编写,并经过本人多次验证。(source code, the code used veilog HDL language, and after I repeatedly verified.)
- 2006-04-06 09:38:19下载
- 积分:1
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craps
this is the source code we have been working on for our project using altera de2 board. the code can be run but some of it miss the end game module, while some doesn t have the complete vga code
- 2014-05-20 15:21:23下载
- 积分:1
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单片机的4 am2901完整的VHDL程序,am2901
4位MCU AM2901的完整VHDL程序,AM2901为主程序,其他为实体库-4 MCU AM2901 complete VHDL program, AM2901-based procedures, other entities, the Treasury
- 2022-12-05 05:15:03下载
- 积分:1
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从两个小的产生更广泛的ALU
Generating a wider ALU from two small ones
- 2022-07-18 07:53:37下载
- 积分:1
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gio_mio_emio_axi
codes for zynq devices
- 2014-06-23 19:00:03下载
- 积分:1
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RISC
URISC的RTL级设计,Verilog代码(Design: URISC RTL Verilog)
- 2019-06-16 23:07:39下载
- 积分:1
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jjj
实现了四bit计数器的功能,使用的是VHDL语言描述(Four-bit counter, using the VHDL language description)
- 2012-12-20 10:53:46下载
- 积分:1