本文件是周立功试验开发板的配套资料，容易学会

这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240-This is my graduation project SVPWM make a permanent magnet AC synchronous motor control system, which apart from a driver SVPWM algorithm, there is a stepper motor controller, as well as QUARTUS7.2 based on the NIOS II control core, through PC serial port can be controlled permanent magnet AC synchronous motor and stepper motor for accurate positioning. The system is more complicated, the use of more knowledge, in the SVPWM algorithm, PID algorithm, stepper motor control, NIOS II serial programming, such as places are worth considering. QUARTUS7.2 compile the best use of the target chip is optional EP1C6Q240

一篇关于FIFO设计以及FPGA设计的文章-FIFO 1 on the design and FPGA design article

说明：  Matlab to hdl code for Least_square testbench

一个NiosII可用的LCD12864 IPcore，含例子-A NiosII available LCD12864 IPcore, with examples

文档包括双线性插值算法和最近邻域算法的详细介绍，以及算法的相关计算。(Documentation includes bilinear interpolation algorithm and the nearest neighbor algorithm which is described in detail, as well as algorithms related calculations.)

这是一个用VHDL语言描述的I2C自动配置模块，使用了来自opencores.org的I2C核，已在altera的cyclone芯片上调试通过-This is a VHDL language used to describe auto-configuration of the I2C module, the use of the I2C from opencores.org nucleus, the cyclone in the altera-chip debugging through

用VHDL语言实现数字钟的设计，要求设计实现一个具有带预置数的数字钟，具有显示年月日时分秒的功能。用6个数码管显示时分秒，set按钮产生第一个脉冲时，显示切换年月日，第2个脉冲到来时可预置年份，第3个脉冲到来时可预置月份，依次第4、5、6、7个脉冲到来时分别可预置日期、时、分、秒，第 8个脉冲到来后预置结束，正常工作，显示的是时分秒。Up为高电平时，upclk有脉冲到达时，预置位加1.否则减1。

VHDL的基本语法，应用，建模，编程示例等...(Introduction to VHDL basic syntax, applications, modeling, programming example and so on ...)

dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim

一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!