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sdram_module3
能够实现16位的SDRAM的读写,没有仿真文件,只有SDRAM读写的源代码,用Verilog编写(can complete read or write sdram, only include Verilog code and no simulation files)
- 2013-11-25 12:43:11下载
- 积分:1
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fm_parcial
this is a simulation fm in simulink mathlab this is one program with pll
- 2012-11-30 10:02:10下载
- 积分:1
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鸟哥的Linux私房菜——基础学习篇(第四版)
全面了解Linux系统,构建服务器,用Vim写写程序(Fully understand the Linux system, build the server, write programs with Vim.)
- 2018-11-02 10:56:59下载
- 积分:1
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- 2022-03-20 01:15:24下载
- 积分:1
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BCH_EncDec_Matlab
bch编解码的完整版,本人已经做过fpga实现,就是按照该程序为原型,绝对可运行(bch decoding the full version, I have done fpga implementation is in accordance with the procedure for the prototype, can certainly run)
- 2011-10-27 21:55:11下载
- 积分:1
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PCIe_Lab(ALTERA-V5PCIe)
这一设计实例深入浅出,介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。
(Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.)
- 2020-12-02 18:39:25下载
- 积分:1
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zhinengchezaishipingxitong
设计了车载视频显示系统,设计了基于FPGA系统结构的车载视频显示电路板,利用FPGA显示视频控制,采集通道时许控制等。(The on-board video display system design, design the system structure based on FPGA video shows the circuit board, using the FPGA show video control, acquisition channel make control, etc
)
- 2011-12-08 15:37:21下载
- 积分:1
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vhdl,双向移位寄存器,实现置数,左移及右移操作
vhdl,双向移位寄存器,实现置数,左移及右移操作-vhdl, bi-directional shift register to achieve set the number of left and right shift operation
- 2022-07-14 16:53:32下载
- 积分:1
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24小时计时时钟
说明: 实现24小时计时,因为位数不够,这里是12进位,可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分:1
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VHDL语言写的波形发生器和sine波形发生器
VHDL语言写的波形发生器和sine波形发生器,一共两个文件,通信开发平台专用。这是一个典型的正玄波发生器程序和一个任意波形发生器程序,大家可以参考学习,对于vhdl入门还是很有帮助的-This
is a typical wave generator Shogen procedures and an arbitrary waveform
generator procedures, Members can take a learning portal for VHDL or
helpful
- 2022-05-29 18:31:54下载
- 积分:1