双向移位寄存器的VHDL源程序,自己做实验编写的可以用 谢谢大家...

经过测试的 VHDL 代码为 18 x 18 位华莱士树乘法器

基于BOOTH的32位快速乘法器的设计源码-BOOTH-based 32-bit fast multiplier design source

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verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)

内有LED译码器，汉明纠错译码器，地址译码器，最高优先译码器，双2－4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code

说明：  rgmii代码编写，实现rgmii接口功能，可进行参考设计(The rgmii code is written to realize the function of rgmii interface, which can be used for reference design)

说明：  matlab bpsk with rayleigh performance expirement

利用verilog驱动LCD1602 本实验是用LCD1602显示英文。（LCD带字库）(//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font))

an 16 bit ripple carry adder

matlab code for JTAG cable checking