Priority encoder in VHDL.

About 1588 PTP protocol xillinx FPGA running code and Software application, and to introduce documents, want to help everyone

数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)

vhdl,序列信号检测模块，此模块检测1110010，可改为任意序列，输出电位为1为检测出，否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0

一些非常有用的程序，均经过调试，让大家一块共享。(Some very useful procedure, have been testing, so that everyone shared one.)

Verilog UART is written in this file

turbo码的verilog程序，有意者请下载。(turbo code verilog procedures Interested parties please download.)

verilog book verilog_2001_ref_guide

直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.

详细设计了异步fifo格雷码中地址码的生效和Man标志的出现

基于FPGA的技术溢出研究程序，只是一个测试程序，大家可以下着用一下。-FPGA-based research process of technology spillovers is only a test procedure, we can next look forward to using.