Xilinx FPGA using leftover multipliers and block RAM

这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)

可以实现对任意波形分任意频，分频加减通过按键实现。-Can be achieved for any arbitrary waveform at frequency, frequency addition and subtraction through the keys to achieve.

说明：  quartus II中文用户教程(英文版的完全翻译）,和一切爱好可编程器件的同仁共勉之(Quartus II Chinese user guide (English version of the full translation) love and all programmable devices colleagues share Zhi)

半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

主要完成ADI公司的DAC（数字-模拟转换器）AD9747的SPI接口及寄存器配置(Mainly to complete ADI' s DAC (digital- analog converter) SPI interface to configure the AD9747 and the register of)

C源碼16C550 串口驅動，使用中斷收送RS232資料(16C550 UART Driver)

reversible Data Hiding in Encrypted Images by Reserving Room Before Encryption

这是一个EOS项目中的GFP成帧结构，能够容错，可以配置字节域(This is an EOS project GFP Framing structure, be able to fault-tolerant, can be configured byte domain)

THE SOURCE REALIZE THE TRANSFORMATION FROM YUV TO RGB

文件用于驱动TFT屏，分辨率800*400，平台为quartus13，芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)