Xilinx FPGA using leftover multipliers and block RAM

提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码(Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code)

xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。 -This simulation uses a AWGN module to include noise as part of the simulation. Prior to running the simulation, the UniSim models for the encoder and decoder must be generated as well as the AWGN module.

verilog实现rtc文档，可用于实现RTC。(verilog realize rtc document can be used to implement the RTC.)

FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)

说明：  从github下载的，能够参考设计AXI4的协议接口(AXI4 Verilog template)

基于fpga和sopc的用VHDL语言编写的EDA的32位Nios CPU嵌入式系统及其DMA设计俄罗斯方块游戏机(FPGA and SOPC based on the use of VHDL language EDA 32-bit Nios CPU and the DMA design of embedded systems Tetris game)

数控分频的一个工程---包括vhdl源程序和编译后产生的相关文件-CNC dividing frequency of a project- including VHDL source code and compile the relevant documents after

说明：  I2C读程序，通过状态机描叙,仿真达到要求(I2C Reading, depicts through the state machine, called Simulation)

以上是VHDL硬件描述语言写的一个简单锝路流水灯程序,希望对刚接触VHDL的朋友有一定帮助-These are the VHDL hardware description language written in a simple flow path lights technetium procedures,刚接触VHDL want to have some friends to help

verilog vga 图像处理(verilog vga)