Xilinx FPGA using leftover multipliers and block RAM

控制步进电机转动，正反转，旋转角度完美掌握。很好用，亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)

基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)

there are exemple in the vhdl

fifo异步串口收发程序 FPGA程序(fifo asynchronous serial transceiver)

用于生成adams或recurdyn所需的路面不平度，用于悬架或其他的仿真(Adams or recurdyn used to generate the required road roughness for suspension or other simulation)

A Mux example written in VHDL.

在开发板EGO1上实现赛车游戏,语言为verilog，内含bits文件(racing game in verilog)

基于DE2开发板，视频图像显示设计源代码，代码调试成功-based DE2 development board ,it is vhdl resourse code

1、用状态机设计A/D转换器ADC0809的采样控制电路，并在数码管上显示转换结果； 2、设置有复位和启动/保持开关，要求 ⑴ 复位开关用来使A/D转换器复位，并做好A/D转换准备； ⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果，即按一下启动/保持开关，启动A/D转换器开始转换，再按一下启/停开关，停止转换并保持结果。 3、采用Verilog HDL语言设计符合上述功能要求的控制电路。(1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request ⑴ A/D converter reset and do A/D conversion ready ⑵ start/hold switch is used to control the A/D converter starts converting or stop the conversion to maintain a continuous result that by clicking Start/hold switch, start the A/D converter to start the conversion, and then Click the start/stop switch stops the conversion and keep the results. 3, using Verilog HDL language designed to meet the functional requirements of the above-mentioned control circuit.)

hdb3 using language VHDL(Indoor using VHDL language)