Xilinx FPGA using leftover multipliers and block RAM

基于FPGA的fsk调制程序，包括载波的生成，nco的设置(FPGA-based fsk modulation procedures, including carrier generation, nco settings)

说明：  数字钟通过verilog实现，并且支持Modelsim仿真(The digital clock is implemented by Verilog and supports Modelsim simulation)

一种基于FPGA的通用微处理器设计-A general-purpose FPGA-based microprocessor designs ....

一个完整的设计DE2_project,希望对大家有所帮助，谢谢ok-A complete design DE2_project, everyone would like to be helpful, thank you ok

基于CPLD的交通灯控制，完成交通灯的功能，校错能力(CPLD-based control of traffic lights, traffic lights to complete the function, the school was wrong capacity)

对赛灵思7系列的三种型号的FPGA进行了综述(xilinx 7 productin overview)

改VHDL代码可以实现超声波测距的功能，其精确度达到US级，可以用七段数码管显示其数值(sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging )

用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。-VHDL hardware description language for FPGA (Cyclone II) configurations VHDL source code.

vhdl cpu芯片逻辑设计的一部分实现 只有一小部分 大家可以看一下 寄存器 加法器之类的(vhdl cpu chip logic design part of its implementation only a little part everry look and see b=about registers adder and so on)

here is a VHDL example