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sdram_hr_hw_4port
这个是DE2上的SDRAM 四个端口的驱动代码,相当实用!(This is a four-port SDRAM on a DE2 driver code, very useful!)
- 2010-07-14 21:21:05下载
- 积分:1
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基于verilog的FIR滤波器程序设计(调试过的)
基于verilog的FIR滤波器程序设计(调试过的)-verilog
- 2023-07-13 23:05:04下载
- 积分:1
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Риторика_Зачетная работа
说明: access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分:1
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uart_byte_rx
说明: libero soc工程,实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)
- 2020-06-21 09:20:01下载
- 积分:1
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Single-CPU
说明: 简单的单周期CPU设计,实现的指令有:算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)
- 2020-06-16 12:28:32下载
- 积分:1
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gpmc_fpga
实现arm与fpga之间通过gpmc总线通信(the device of fpga)
- 2015-10-27 16:44:25下载
- 积分:1
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一位LED显示的VHDL程序,挺简单的,买的开发板里面带的
一位LED显示的VHDL程序,挺简单的,买的开发板里面带的-An LED display of the VHDL program, quite simply, to buy development board inside the zone
- 2023-07-18 00:45:02下载
- 积分:1
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本设计是针对LEON3 Altera Nios II startix2
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the
- 2022-05-18 19:00:04下载
- 积分:1
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OFDM信道估计的LS算法的FPGA实现
本程序用于实现OFDM信道估计的LS算法的硬件仿真,基于FPGA开发的VHDL编写,给出了各模块的仿真波形图,供大家交流参考。
- 2023-02-25 09:55:04下载
- 积分:1
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RISC
说明: URISC的RTL级设计,Verilog代码(Design: URISC RTL Verilog)
- 2019-06-16 23:07:39下载
- 积分:1