This is the design of the divider module EDA. Can achieve three different freque...

此VHDL语言程序可以控制液晶屏幕任意动画播放(The VHDL language program can control the LCD screen any animation)

说明：  HDB3编码Quartus2 10.0的工程，modelsim仿真，有实物图、仿真图以及源程序，适合做通信原理课程设计的同学参考使用(HDB3 encoding Quartus2 10.0 project, modelsim simulation, there are physical map, simulation diagrams and source code, suitable for students of communication theory courses designed for reference use)

本程序描述了七分频数字电路，程序经过仿真，可以使用。该程序的设计方法为常用的奇数分频设计方法，简单易懂，具体方法描述网上很多，此外设计其他类似的奇数分频电路时，可以直接改动程序中相应的参数即可。文件中工程已经建好，可以用quartus II直接打开

24位x24位的乘法器 十分详细24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器24位x24位的乘法器(24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplication Explorer 24-bit x24 multiplier 24-bit x24-bit multiplier)

基于VHDL语言的波形发生器编程设计，能够实现常用波形的产生。(Waveform generator design based on VHDL programming, to achieve common waveform generated.)

NIOS II IDE 编程， 定时器测试程序，仅供参考。-NIOS II IDE programming timer testing procedures, for information purposes only.

Verilog实现的USB程序，用ISE打开工程文件即可-Verilog implementation USB program, open the project file with the ISE can be

代码是一个复数乘法器，两个复数相乘，只用到了2个实数相乘，运算量少(Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less)

DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)

modbus通讯必须的校验码生成器，可以直接使用(modbus crc16/8 free use)