该代码在信令模块MK50H27 CPLD第七满足（Xilinx 95144）罗…

RS(255,223)编码器程序 从一本书上看到的，很不错的(RS(255,223) encode , very good good good )

Introduction to learn laboratry with altera quartus II 9.1

一个液晶灯的小程序。我没有写信。我只负责调试。适用于ACEXEP1K30QC208-3。我运行模拟器，标记连接销。我接下来在电路板上试了试，没有问题。实验中使用的板兄弟把CLK1的TESTOUT3改成了合唱或0。新人在线帮助是每个人的责任。

基于FPGA的视觉电生理图像刺激系统的设计(Based on the design of FPGA visual electrophysiology image stimulation system)

使用VerilogHDL语言加上IP核产生PWM调制波，占空比和频率可调。(The PWM modulation wave, duty cycle and frequency can be adjusted by using VerilogHDL language and IP kernel..)

uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps

buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键-buffer_display is 4X4KEYPAD output module. It showed six consecutive Press

程序用VHDL实现： 频率合成，DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM

使用Verilog实现的AD采样，很有用的！(Implemented using Verilog AD sampling, very useful!)

基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2