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e1framer
E1 deframmer and Frammer.
- 2013-02-25 19:43:35下载
- 积分:1
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用VHDL写的交通灯控制源码,原创,希望对大家有所帮助
用VHDL写的交通灯控制源码,原创,希望对大家有所帮助-Use VHDL to write a traffic signal-controlled source, originality, and they hope to help everyone
- 2022-12-31 00:45:12下载
- 积分:1
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自动打铃系统 附带时钟 定时打铃 整点打铃
自动打铃系统 附带时钟 定时打铃 整点打铃-Auto-play Ling System
- 2022-08-26 11:38:33下载
- 积分:1
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FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
FPGA实现的LCD接口,VHDL编程,FPGA芯片为ALtera公司的EP2c35-FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera
- 2022-09-14 14:30:09下载
- 积分:1
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VHDL I2C模式
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- 2022-01-25 13:58:21下载
- 积分:1
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单相逆变simulink仿真
说明: 利用Matlab/simulink实现电力仿真,其中单相逆变可用于多电平变流器的基础使用,本案例提供了不同调制手段实现逆变的模型(Matlab / Simulink is used to realize power simulation, in which single-phase inverter can be used as the basis of multi-level converter. This case provides the inverter model with different modulation means)
- 2019-11-12 15:03:55下载
- 积分:1
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CCPRRIzipP
一种基于CPRI标准的WCDMA NoddeB射频光纤拉远接口FPGA设计.pdf
(CPRI compliant the WCDMA NoddeB RF fiber pull far from the interface of the FPGA design. Pdf)
- 2012-07-19 22:29:39下载
- 积分:1
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ymq.ppt.tar
掌握二-十进制(BCD码)异步计数器的工作原理和设计方法;
掌握中规模集成二-五-十进制异步计数器74LS90的功能及其应用;(Master II- Decimal (BCD code) the principle and an asynchronous counter design grasp the scale of integration in two- five- Decimal asynchronous counter 74LS90 features and applications )
- 2011-04-26 21:53:37下载
- 积分:1
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fft
说明: 用VERILOG语言实现的频谱分析仪(FFT)(VERILOG language with the Spectrum Analyzer (FFT))
- 2009-08-09 16:30:23下载
- 积分:1
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基于altera系列芯片lvds接口的fpga设计 verilog源码
基于altera系列芯片lvds接口的fpga设计 verilog源码-Series altera-based chip interface lvds source fpga design verilog
- 2023-08-31 17:40:04下载
- 积分:1