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利用VHDL语言实现8位到32位的双向数据转换
利用VHDL语言实现8位到32位的双向数据转换-use VHDL 8-32 two-way data conversion
- 2022-03-23 16:58:55下载
- 积分:1
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SRAM
进阶实验之SRAM测试,由verilog编写,可直接对sram进行存写(Advanced SRAM test experiments, written by the verilog, can be stored directly on the sram write)
- 2011-08-18 01:58:56下载
- 积分:1
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modulation-and-demodulation
调制与解调系统的FPGA设计实现,包括2-ASK调制和解调,2-FSK调制和解调,2-PSK调制和解调,QPSK调制和解调,PPM调制和解调的verilog源代码。(FPGA design implementation of modulation and demodulation system, including 2-ASK modulation and demodulation, 2-FSK modulation and demodulation, 2-PSK modulation and demodulation, QPSK modulation and demodulation, PPM modulation and demodulation verilog source code .)
- 2021-04-09 09:29:01下载
- 积分:1
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一种使用modelsim6简单的解码程序
A program for a simple decoder using ModelSim6
- 2022-02-06 04:44:14下载
- 积分:1
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宝宝挂
最新热血江湖外挂,需要的可以下载,游戏开心热血江湖应用辅助(Yulgang latest plug-in needed to download, games happy))
- 2020-06-23 09:20:02下载
- 积分:1
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使用Veriolog hdl 编写手机屏测试程序.
使用Veriolog hdl 编写手机屏测试程序.-Veriolog hdl prepared to use cell phone screen test.
- 2023-04-25 00:20:03下载
- 积分:1
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include UART port of VERILOG source, the program tested in FPGA, as chip design,...
包含UART口的VERILOG源程序,该程序在FPGA上验证通过,可作为芯片设计,或FPGA设计的一个完整IP核,硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
- 2022-06-01 13:44:15下载
- 积分:1
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VHDL 编写的RAM例子
VHDL 编写的RAM例子-RAM prepared VHDL example
- 2023-03-23 05:20:03下载
- 积分:1
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OFDM_QPSK
给予QPSK调制的OFDM例程,简单明了的表述了OFDM的通信原理(Given OFDM QPSK modulation routine, simple expressions of OFDM communication theory)
- 2013-08-15 14:26:43下载
- 积分:1
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matlab_dspbuildings
matlab dsp building 工程欢迎下载(matlab dsp building )
- 2009-12-30 09:17:38下载
- 积分:1