This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Educati...

Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.

最大最小值寻找程序，可以实现自动查找最大值与最小值(min_max_finder)

良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)

fpga 设计全攻略，很好的fpga入门提高资料(the fpga design Raiders, good fpga the Getting Started improve data)

使用QuartusII软件，利用VHDL语言设计实现CPU,其中包含时序图仿真。(Using software QuartusII, using VHDL language to design the CPU, which contains sequence diagram simulation.)

FPGA实现反正切功能，工程原件，包括测试文件，能够很好实现该功能(FPGA implements arctangent function, original engineering)

design ram v8051 for project

此练习的目的是要了解如何连接简单的输入和输出到 FPGA 芯片的设备和 实现电路，使用这些设备。我们将作为投入 DE2 系列主板上使用 SW17

基于FPGA 黑金ALINX 515的 ADDA采样模块源码（需调试）(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)

This source is used to control 7 segments on FPGA boad