ad9983的检测视频信号的code及其project 用的是xilinx 的virtex4 但不包括I2C...

VGA彩条信号显示控制电路设计,能通过vga显示横条纹竖条纹棋盘条纹(VGA color signal display control circuit design)

说明：  本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS (6,4) encoder. Using the ISE software Verilog HDL language for each module is described, and then compile, simulation in software, the ultimate realization of the RS (6,4) encoding, after downloading by chipscope data acquisition, the analysis with the simulation results meet the design requirements.)

基于FPGA的运动控制系统设计，包含位置、速度控制等(motion control)

programe reverse a string in c

。给出了时域滤波的基本原理以及通常采用的 IIR 椭圆地物杂波滤波器的设计方法。重点研究了回归滤波器这一时域滤波算 法。从正交多项式的拟合出发，给出了回归滤波器抑制地物杂波的基本原理及 其滤波实现过程。通过对回归滤波器的计算复杂度的研究，寻找使回归滤波器 计算量最小的正交多项式。分析了回归滤波器频率响应特性，比较了回归滤波 器与IIR 椭圆地物杂波滤波器的计算复杂度。利用仿真的雷达信号，分析了回 归滤波器的地物杂波抑制性能。回归滤波器实际上是一高通滤波器，它在滤掉 低频地物杂波的同时，对落在滤波器阻带内的天气回波信号同样会造成衰减。 在天气回波信号谱宽固定的情况下，通过改变天气回波信号的平均多普勒频率， 分析了回归滤波器对它的衰减情况。在基于一组实际采集的雷达信号的基础上， 给出了回归滤波器的地物杂波抑制比随着滤波器阶数的变化情况。(Firstly, this dissertation introduces the research background and significance of ground clutter suppression, analyzes the characteristics of the ground clutter and weather signals in the Doppler weather radars and simulates Doppler radar echo signals (It includes ground clutter, weather echo signals and the mixture of them). The simulated signals are used later to study the time and frequency domain ground clutter suppression. Secondly, this dissertation talks about the time domain filtering, gives the basic theory of time domain filtering and describes the design method of the usually used fifth-order elliptic infinite impulse response (IIR) ground clutter filter. In the time domain, the work focuses on the regression filter. From the orthogonal polynomials fit, this dissertation gives the basic theory of the regression filter for ground clutter suppression and the filtering process using a regression filter. Through the study of the computational complexity of regression)

VHDL code of a counter Code VHDL d un compteur

关于LDPC解码的verilog程序，包含设计代码和验证环境(LDPC decoding on verilog procedures, including the design code and verification environment)

Simulation and Synthesis Techniques for Asynchronous FIFO Design

Verilog UART is written in this file

使用verilog语言描述的二阶巴特沃斯IIR滤波器，程序中有参数说明，已经运行通过(Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter description has been run through)