用FPGA实现数字锁相环，开发环境为ISE

该PPT是一个内部教学资料，想学习EDA技术的朋友可以看看这个教学资料。-The PPT is an internal teaching materials, want to learn EDA technologies friends can look at the teaching and learning materials.

dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, water lamp demonstration. code test.

fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

16*16点阵横向移动显示！采用QUARTUS II 9.0编译通过！(16* 16 dot matrix display lateral movement! Compiled by using QUARTUS II 9.0!)

Implementation of Serial Infrared decoder for low-speed IrDA communications.

说明：  LTE is an abbreviation for Long Term Evolution.

report for a report for a class

VHDL implementation using mouse and monitor

使用DE2实现DDS，步骤简单，配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)

一款在Verilog实现的吃豆人游戏，采用VGA接口，在Nexys3开发板上运行无误。(A pac-man game implemented via Verilog, using VGA interface, perfectly run on Nexys 3)