利用vhdl编写的双端口Ram程序，不带数据纠错处理

FPGA控制外边led，并实现跑马灯等多种效果，用户可以自行控制(FPGA control outside led)

说明：  FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)

说明：  combinatorial modules

verilog编写的流水线模块-Verilog modules prepared by the Pipeline

说明：  FPGA 学习实例 动态时钟、面积、速度优化相关代码(Codes related to dynamic clock, area and speed optimization for learning examples of FPGA)

一个简单的探测110三位的探测器，用逻辑图和vhdl描述，包括实验报告和测试图。-a simple survey of 110 three detectors, and a logical map vhdl description, including reports and experimental test plan.

本程序实现两个整数平方和相加并且输出结果-the program two integers and the sum of squared output

SHA256加密过程,非常详细，内附原码，还有文档，很可用~(SHA256 encryption process, very detailed, containing the original code, as well as documents, it is available ~)

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计-Simulation using VHDL language music design music design simulation VHDL language

BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)