verilog，4、5分频器，5分频器占空比3：2

用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.

本verilog代码通过IIC总线实现了对 PCF8591AD、DA转换芯片的控制。适用于FPGA，亲测可用。(this is used for FPGA to control PCF8591(AD/DA) chip by verilog.)

fpga key test 入门 xilinx 黑金的板子(fpga key test xilinx)

MATLAB Filter Design HDL Coder Simunlink HDL Coder Xilinx ISE Webpack

fifo异步串口收发程序 FPGA程序(fifo asynchronous serial transceiver)

安富利SP605开发板ISE12.4版本的XBD文件，里面包括了开发板所有的接口，包括硬件和软件设计(Avnet SP605 development board ISE12.4 version XBD file, which includes the development board all interfaces, including hardware and software design)

作为一个简明的教程，主要宗旨是让初学者快速地了解FPGA/SOPC（可编程片上系统）开发的流程。-As a simple tutorial, the main purpose is to enable beginners to understand Express FPGA/SOPC (system on programmable chip) development process.

该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用(The program describes the simulation and the function and role of a mole finite state machine)

vhdl编写的硬件乘法器-prepared by the VHDL hardware multiplier

说明：  很好的免费学些 verilog教程 欢迎下载(Learn a good free download verilog tutorials welcome)