16 point radix 2

用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。()

一个用于锁相环开发的资料，请作为参考！-A phase-locked loop for the development of the information, please as a reference!

FPGA设计流程指南 介绍基本的设计方法-FPGA Design Process Manual

Vivado同步计数器VHDL设计 具有异步复位和同步预置数功能 同步计数器同步计数器同步计数器(The Vivado synchronous counter VHDL is designed with asynchronous reset and synchronous preset function, synchronous counter, synchronous counter and synchronous counter.)

同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated

it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scripts, pdfs, netlists etc. and a MIPS IP package

说明：  对于一串二进制数前置零的计数的Verilog程序(For a string of binary zero count Verilog pre-procedure)

包括很多格式的85基准电路，不需手动转换，可以供学者自行选用。(This resource including many formats 85 banchmack circuit, without manual conversion, you can choose for the scholar.)

说明：  AXI verilog designs with testbench: AXI-lite, AXI, AXI-stream

VHDL实用教程，详细介绍VHDL语法、开发环境、应用实例等。。。(VHDL course)