程序是用硬件描述语言（VHDL）实现：4×4键…

完成GPS的IRIG_B码解码，已经模块化，并且有详细的中文注释(Completed the GPS IRIG_B of decoding modular, and there are detailed notes in Chinese)

配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

说明：  FPGA串口实现。 发送和接受数据功能代码(FPGA serial interface. Send and receive data function code)

verilog实现闪烁灯和流水灯dechengxu-verilog liushuideng shanshuodeng chengxu

此源码为线性相位滤波的vhdl源码与设计心的体会，理论分分析与工程实践总结相结合，有非常大的参考价值 可直接使用。 (The source for the linear phase filter VHDL source code and design of the heart experience, theoretical analysis to summarize the combination of engineering practice, a very large reference value can be used directly.)

基于xilinx spartan 3E开发板，通过旋转编码器实现流水灯的左右移动闪烁变换。(Based on the Xilinx Spartan 3E development board, the left and right flicker transformation of the flow lamp is realized by the rotary encoder.)

一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析-A complete signal test procedures, the various indicators of signal integrity testing, and analysis of

基于fpga的4*4键盘扫描verilog程序-du to fpga 4*4 keyscan verilog

扰码器的verilog实现,参考802.11a相关标准(Scrambler in verilog implementation)

verilog写的LnE算法，可用于计算指数和对数(Verilog written in LnE algorithm, can be used to calculate the index and the logarithm)