基于超大规模集成电路内建自测试SOC

说明：  这是一个用Verilog语言编写的一组程序，主要是熟悉开发板的应用，以及verilog语言(This is a Verilog language with a set of procedures, mainly familiar with the application development board, and the verilog language)

EasyWifiRadar.zip r ok

中值滤波实现。选择在Vivado软件上采用Verilog语言来编写中值滤波算法，搭建出完整的数据处理系统架构，通过仿真和验证来判断数据的处理效果，并在实际的设计过程中根据出现的问题提出解决方案。(Median filter implementation. The author chose Verilog language to write the median filter algorithm in Vivado software, built a complete data processing system architecture, judged the data processing effect through simulation and verification, and proposed a solution according to the problems in the actual design process.)

多功能数字时钟 功能齐全 vhdl fp-Multi-functional digital clock vhdl fpaa

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)

用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.

简易电子钟的设计（verilog HDL）(Simple design of the electronic clock (verilog HDL))

GPS信号结构,C/A码产生方式及其测距码研究(GPS signal structure and ranging code research)

基于FPGA的VGA彩条显示 可用PAXplusII仿真-FPGA-based VGA color display available PAXplusII Simulation of

32位全加器，另有一个采用流水线的版本，是基于verilog语言的，很实用，希望对大家有所帮助(32-bit full adder, while a pipelined version，code is based on verilog language, it is practical, we hope to help)