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LDPC码校验节点(checknode)进行奇偶校验方程时的vhdl编程,硬件语言实现...
LDPC码校验节点(checknode)进行奇偶校验方程时的vhdl编程,硬件语言实现-LDPC check nodes (checknode) carried out at the time of parity equation VHDL programming, hardware language
- 2022-02-26 15:07:26下载
- 积分:1
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SoC sample Code using Altera Xcaliber, good usefull SoC.
SoC sample Code using Altera Xcaliber, good usefull SoC.
- 2022-02-04 17:46:18下载
- 积分:1
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sample_SPI
这是一个瑞萨R78/G13的SPI演示程序,详细的放置了说明,很有用的源码(This is one of the SPI Renesas R78/G13 demonstration program, placed a detailed description of very useful source)
- 2013-09-03 02:59:19下载
- 积分:1
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breath
说明: 利用verilog写的PWM 程序,来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)
- 2020-06-17 04:40:01下载
- 积分:1
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modulation-and-demodulation
调制与解调系统的FPGA设计实现,包括2-ASK调制和解调,2-FSK调制和解调,2-PSK调制和解调,QPSK调制和解调,PPM调制和解调的verilog源代码。(FPGA design implementation of modulation and demodulation system, including 2-ASK modulation and demodulation, 2-FSK modulation and demodulation, 2-PSK modulation and demodulation, QPSK modulation and demodulation, PPM modulation and demodulation verilog source code .)
- 2021-04-09 09:29:01下载
- 积分:1
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dds
说明: 基于fpga的函数发生器设计通过fpga实现正弦波输出(基于fpga的函数发生器)
- 2009-08-01 08:47:29下载
- 积分:1
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dac
FPGA的驱动并行接口的DAC程序,效率较高。(FPGA-driven parallel interface of the DAC process more efficient.)
- 2011-08-04 21:48:11下载
- 积分:1
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liushui
本程序实现流水线功能,您可根据自己需要更改参数,试用芯片xilinx,用verilog语言编写(This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language)
- 2016-03-07 09:26:28下载
- 积分:1
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Arty-Z7-20-hdmi-out-master
说明: Arty Z7 20 HDMI output
- 2021-04-24 15:18:47下载
- 积分:1
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Altera的CycloneIII Start Board,使用的PFGA是3C25,包括原理图和PCB,用Cadence Allegro打开...
Altera的CycloneIII Start Board,使用的PFGA是3C25,包括原理图和PCB,用Cadence Allegro打开-Altera
- 2022-10-05 01:50:03下载
- 积分:1