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verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用....
verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
- 2022-08-24 07:12:53下载
- 积分:1
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ISPPCBforFPGA
Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB(Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB)
- 2009-12-14 16:55:35下载
- 积分:1
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华勒斯树结构的8位修正展位乘数
应用背景Booth乘法器实现快速乘法algorithm.mainly用于通信和DSP组成的3块摊位重新编码,华勒斯树和超前进位addder关键技术超大规模集成电路设计,通信和DSP的应用,芯片设计,VHDL,Verilog程序,加法器和乘法器
- 2022-02-04 19:57:10下载
- 积分:1
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altera several new FPGA configuration methods and the use of experience
altera的几种新型的FPGA的配置方法和使用心得-altera several new FPGA configuration methods and the use of experience
- 2022-05-09 07:27:04下载
- 积分:1
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Ping_pong_Sparten3e-master
说明: FPGA实现乒乓球游戏 代码及仿真 VGA实现(FPGA realizes table tennis game code and simulation VGA implementation)
- 2019-05-06 20:22:13下载
- 积分:1
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qam_64
Verilog语言下QAM调制的DDS实现(The QAM Modulation DDS achieve)
- 2021-02-20 11:59:43下载
- 积分:1
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频率计
说明: 1、能正确显示输入信号频率;
2、测量频率范围为1Hz ~ 999999Hz;
3、测量结果以十进制数字显示;
4、能测量幅值较小的信号频率;
5、有自动刷新输出数据的功能(如5s刷新一次);
6、有自检模块(如产生100Hz的校准方波);(1. It can correctly display the input signal frequency;
2. The frequency range of measurement is 1Hz ~ 99999hz;
3. The measurement results are displayed in decimal;
4. It can measure signal frequency with small amplitude;
5. It has the function of automatically refreshing the output data (e.g. once in 5S);
6. Self checking module (such as generating 100Hz calibration square wave);)
- 2020-03-28 16:37:56下载
- 积分:1
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VGAtuxiangxianshi
用FPGA实现 VGA显示的图像显示控制器设计
用VHDL实现 硬件实现是屏幕上面出现彩色条纹(VGA display with FPGA image display controller design
Using VHDL hardware implementation is colored stripes appear above the screen)
- 2014-05-19 14:07:57下载
- 积分:1
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Automatic-washing-machine-controller
全自动洗衣机的控制器。
1.洗衣机的工作步骤为洗衣、漂洗和脱水三个过程,工作时间分别为:洗涤10秒,漂洗5秒,脱水5秒;
2.用一个按键实现洗衣程序的手动选择:A、单洗涤;B、单漂洗;C、单脱水;D、漂洗和脱水;E、洗涤、漂洗和脱水全过程;
3.用显示器件显示洗衣机的工作状态(洗衣、漂洗和脱水),并倒计时显示每个状态的工作时间,全部过程结束后,应提示使用者;
4.用一个按键实现暂停洗衣和继续洗衣的控制,暂停后继续洗衣应回到暂停之前保留的状态;
(Automatic washing machine controller. 1 washing machine work steps for the laundry, rinsing and dehydration three processes, working hours are as follows: washed for 10 seconds, rinse for 5 seconds, dehydrated five seconds 2 with a button to manually select the program to achieve laundry: A, single-washing B, single rinse C, a single dehydration D, rinsing and dehydration E, washing, rinsing and dehydration the whole process 3 with a display device display the working status of washing machine (laundry, rinsing and dehydration), and each state countdown show working hours, after the whole process should prompt the user 4 laundry with a button to pause and continue control of laundry, laundry should be back after a pause pause before continuing to retain the state )
- 2020-11-11 16:29:44下载
- 积分:1
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一种新的FIFO实现方法,verilog描述,通过modelsim 6.0 仿真,Quartue综合...
一种新的FIFO实现方法,verilog描述,通过modelsim 6.0 仿真,Quartue综合-FIFO realize a new method, verilog description, modelsim 6.0 through simulation, Quartue integrated
- 2023-01-18 15:40:03下载
- 积分:1