Booth Algorithm Based Squarer Design

合并单元内GPS同步时钟的检测 合并单元内GPS同步时钟的检测-Combined unit GPS clock synchronization detection unit merger GPS synchronized clock detection

基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)

此程序完成了FLASH的擦除，读写的功能，并通过USB芯片FT245传送到PC...............................................................................................................................................................................................

自动售货机的状态机实现 自动售货机的状态机实现(this is a automachine)

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第四个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The fourth document

使用ISE软件实现OFDM通信系统的框架搭建，完成上板前的仿真工作(Realization of OFDM communication system with ISE software)

CAN总线开发代码，FPGA与sja1000通信，可实现CAN的接收和发送。(The FPGA and the sja1000 CAN bus development code, communication, which CAN realize the CAN send and receive.)

一个简单的微处理器的实现，能够进行几种常见的操作，对于熟悉计算机的工作原理很有帮助，并且附有详细的设计报告和设计思路。在word文档最后给出了源代码。-a simple microprocessor to achieve, for several common to the operation of the computer for those familiar with the working principle helpful, and with the detailed design reports and design ideas. The word is the final document source code.

软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 这个实例实现通过ModelSim工具实现一个具有“百分秒，秒，分”计时功能的数字跑表； 2. 工程在project文件夹中，双击paobiao.ise文件打开工程； 3. 源文件在rtl文件夹中，paobiao.v为设计文件，paobiao_tb.tbw是仿真测试文件； 4. 打开工程后，在工程浏览器中选择paobiao_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，若正确安装ModelSim，系统将自动打开ModelSim进行行为仿真，运行仿真即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.01. Realize this instance through the ModelSim tool realize a

说明：  功能是（用Verilog语言的，内有比较详细的注释）： （1）计数器的功能是从0到9999计数，并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块). （2）该计数器有一个1个nclr和一个adj_plus端，在控制信号的作用下（见下表），计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块. 计数器的功能表 nclr adj_minus 功 能 0 0 复位为0 0 1 递增计数 1 0 递减计数 1 1 暂停计数 (Function is (with Verilog language, the more detailed comments): (1) counter function is from 0 to 9999 counts, and are able to form a decimal number on the seven-segment LED display (including the seven-segment LED display module). (2) The counter has a one nclr and a adj_plus side, under the action of the control signal (see below), the counter has reset, increase or decrease of count pause function. Complete the preparation of the above program modules. Counter function menu nclr adj_minus reset 0 0 0 0 1 1 0 counts counting suspended Count 1 1)