NCO of the VHDL process is the use of nuclear

24bitAD数据采样进行串并转换，并行输出。另包括24位DA并串转换，串行输出。(24bitAD data sampling and converted to strings, parallel output. Other notable features include 24-bit DA and string conversion, serial output.)

Fixed-point base-2 logarithm (DW_log2) // Computes the base-2 logarithm of a fixed point value in the // range [1,2).

一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer

Programmable IIR Filter written in Verilog and its respective modules.

VHDL与Verilog的比较-VHDL and Verilog comparison

SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)

说明：  使用FPGA实现中值滤波算法，能够使数据直接使用该系统对数据进行中值滤波。(FPGA is used to realize the median filtering algorithm, which can make the data directly use the system for median filtering.)

本程序实现数字钟系统，有整点报时功能，可显示切换年月日，定时功能(Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function)

基于fpga的DDS程序 可输出正弦波 方波 三角波 锯齿波(DDS program based on FPGA can output sinusoidal square wave triangular wave sawtooth wave)

作为一个简明的教程，主要宗旨是让初学者快速地了解FPGA/SOPC（可编程片上系统）开发的流程。-As a simple tutorial, the main purpose is to enable beginners to understand Express FPGA/SOPC (system on programmable chip) development process.