Xilinx CPLD源代码，使用XC9500系列CPLD,驱动液晶

sigmoid函数硬件实现，verilog代码及其测试用例(Sigmoid function hardware implementation, verilog code and test cases)

VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source

清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，音乐计算器，完成两个三位数的运算，有注释，很强大！！(Verilog, QuartusII run correctly, can be downloaded to the FPGA, music, calculator, completed two three-digit operations, there are notes, very powerful! !)

四位密码锁，移位显示，可以设置和更改密码。-4 lock, shift, it can be set up and change your password.

FPGA连接PCI9504的电路图。以及PCB文件(FPGA connected to the circuit diagram of the PCI9504. And PCB files)

在开发板EGO1上实现赛车游戏,语言为verilog，内含bits文件(racing game in verilog)

介绍了基于Altera 公司的CPLD 芯片FL EX10 K,以及利用VHDL 语言实现多位二进 制码转换成8421BCD 码的原理、设计思路和软件实现。-Introduction based on Altera

xlinx官方的iic和spi接口的描述-IIC and xlinx official description of spi interface

modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program

This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.