Xilinx CPLD源代码，使用XC9500系列CPLD,驱动液晶

以太网总线源代码，里面有详细的文档说明，已经过FPGA验证。-Ethernet bus source code, which has a detailed document that has been FPGA verification.

本文是Altera公司编写的dspbuilder的设计方法，但是是英文原版的(This article is prepared by Altera Corporation dspbuilder design method, but it is the original English edition of)

一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的PCI位码文件及配置程序。-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of the PCI code files and configuration procedures.

说明：  This is code of UVM CALLBACK function.

说明：  Xilinx ISE License集合，包含Vivado、ise的破解license，安装ISE后loading license即可完成，最全的器件库(Xilinx ise license Collection, including Vivado and ISE cracking licenses. After ISE is installed, the loading license can be completed, which is the most complete device library.)

用verilog语言编写的4位算术逻辑单元ALU,功能参考74181，包含.v文件以及测试用.vwf文件(Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document)

数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on

MIG IP控制DDR3读写测试，于MIG IP核用户接口时序较复杂，这里给出扩展接口模块用于进一步简化接口时序。(MIG IP controls DDR3 reading and writing tests, and the time sequence of MIG IP kernel user interface is more complex.)

I2C总线在可编程逻辑器件上实现的VHDL源码-VHDL source codes for realizing I2C

vhdl project at sbu uni in iran uart