In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Ver...

对MAX5250芯片进行控制，实现DA转换输出。(Controlling MAX5250 Chip)

正弦波VHDL语言~~~ ~~~ ~~~`-Sine wave VHDL language ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ `

动态获取CPU使用率源码 可以加到压力测试里(Dynamic access to CPU use the source code )

Verilog编写的串口通讯下解码状态机(Verilog serial communication prepared under the decoder state machine)

本例为DAC0832接口电路VHDL原代码-The DAC0832 Interface Circuit Example for VHDL source code

FPGA控制SJA1000实现CAN协议 适合深入学子FPGA的学生 很不错(FPGA control the SJA1000 CAN protocol for in-depth realization of the students are very good students FPGA)

This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)

AM modulated learning ladder

说明：  FPGA 读写 SRAM 存储块，verilog代码(Read and write SRAM memory block and Verilog code in FPGA)

中科院VHDL学习资料，很好的东西，希望对大家有用-Chinese Academy of Sciences VHDL learning materials, a very good thing, everyone would like to be useful