In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Ver...

基于FPGA的VHDL可以产生不同的音调,象音乐一样-based FPGA VHDL can produce different tones, like the same music

四位全家器的VHDL语言模块，已经在ISE8.1上经过测试通过-family of four VHDL modules, has been tested on ISE8.1 through

cvery high compatibles for quartus

8位有符号编码的整数基改性

基于FPGA实现蜂鸣器播放音乐的功能 使用芯片为EP2C8Q208C8N,使用普通蜂鸣器，由于频率不同可实现放歌功能，本例设计的是《友谊地久天长》，使用Verilog语言编程，本例子有工程文件、仿真、波形，经过测试可以使用。(Play music based on FPGA buzzer functions using chip EP2C8Q208C8N, using ordinary buzzer, since the frequency of different functions can be realized sing, in this case the design is " Auld Lang Syne" , using Verilog language programming, this project examples files, simulation, waveform, tested can be used.)

verilog语法说明，包含verilog golden reference guide，verilog 2001语法(verilog golden reference guide)

SoC sample Code using Altera Xcaliber, good usefull SoC.

FPGA经验总结：时序是设计出来的 我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)

这是一个计算器的Verilog代码，可实现加减乘除等基础功能(calcultor for you to do some reserches.)

利用FPGA实现USB芯片CY7C68013与上位机的进行通信的系统，代码采用VHDL语言实现，利用状态机实现FPGA控制USB的数据传输，传输时序采用SLAVE FIFO实现