SoC sample Code using Altera Xcaliber, good usefull SoC.

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

---------------------------------------------------------------------------------- -- Company:       VISENGI S.L. (www.visengi.com) - URJC FRAV Group (www.frav.es) -- Engineer:      Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com) -- -- Create Date:    12:39:50 06-Oct-2008 -- Pr

这是一个计算机组成原理综合性实验：设计8位cpu。该cpu是8bit的代码，包含有4个寄存器，一个存储器，还有alu以及控制器。一共可以实现16条指令。(This is a computer composition principle of comprehensive experiment: Design 8 cpu. The cpu is 8bit code contains four registers, a memory, as well as alu and controllers. A total of 16 instructions can be achieved.)

利用verlilog hdl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！-Verlilog hdl programming language to use to complete the 8051 core, very much worth learning hardware description language of the people to see!

VHDL_modelling_guidelines是vhdl建模开发的指导资料-VHDL modeling VHDL_modelling_guidelines is guiding the development of information

dds数字移相信号发生器,功能齐全通过验证-dds digital shift Signal Generator, full-featured validated

this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

FPGA生成伪随机数,希望对加密的童鞋有用(FPGA generates pseudo-random numbers, we want to be useful)

MMC卡的VHDL源代码实现，经过大批量生产验证-MMC card VHDL source code to achieve, through large-scale production test

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像形态学部分,腐蚀,膨胀,细化算法(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image morphology section, corrosion, swelling, thinning algorithm)