SoC sample Code using Altera Xcaliber, good usefull SoC.

Ethernet 10GE MAC 以太网10G的MAC Verilog代码实现(Ethernet 10GE MAC)

从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code

verilog hdl 编写的64点fft代码，适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)

基本的usb驱动程序的编程方法,值得一看.-Basic programing method for USB driver, worth reading

说明：  altera发布的开源8b10b源代码，vhdl语言描述(altera released the source code open source 8b10b, vhdl language description)

用blockram实现移位寄存器，开发语言为verilog hdl(Shift register with blockram achieve the development language for the verilog hdl)

内插成型滤波器的FPGA实现，可根据需要配置不同的内插倍数，Quarter II环境编译，可直接使用(Interpolation shaping filter FPGA, can be equipped with different interpolation factor, Quarter II compiler environment, can be used directly)

ahb to apb master verification

利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed source code as well as the design process, the module

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )