SoC sample Code using Altera Xcaliber, good usefull SoC.

基于quartus 的一些程序 都是verilog 还是比较有用的 -Based on some of the procedures Quartus Verilog are still quite useful

verilogHDL语言编写，简单的FPGA脉冲程序，初学者必备。(verilogHDL language, a simple FPGA pulse program, beginners must.)

SAA7113 ＦＰＧＡ开发实例，非常经典(The SAA7113 FPGA development examples, very classic)

说明：  用VHDL语言实现电子钟(Using VHDL language electronic bell)

用Verilog语言实现QPSK调制，QPSK是一种数字调制方式。它分为绝对相移和相对相移两种。 (Verilog language using QPSK modulation, QPSK is a digital modulation. It is divided into absolute and relative phase shift of the phase shift of two.)

GBT 15946-2008 GPIB可编程仪器标准数字接口的高性能协议 概述 (GBT 15946-2008 GPIB Programmable Instruments standard digital interface for high-performance protocol Overview)

基4FFT原理及MATLAB实现，基本原理，编程思想等(base——4 FFT principle and MATLAB implementation, the basic principles of programming ideas, etc.)

EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals. )

基带数字信号通过成形滤波（选用升余弦滚降函数）然后进行载波调制(Base-band digital signal through the shaping filter (raised cosine roll-off optional function) and then proceed to carrier modulation)

基于芯片MAX502的十二位并行DAC芯片的程序，利用FPGA中的ROM查表进行数据存储-Based on 12 of the MAX502 chip DAC chips in parallel procedures, the use of FPGA in the ROM look-up table for data storage