基于FPGA 的usb传输

通过UART从PC主机读取图片数据，并完成图片在VGA显示器上的显示-through UART from the host PC to read image data, and complete picture of the VGA display on the show

基于FPGA的Verilog语言实现的六十进制计数器(FPGA-based Verilog language implementation of six decimal counter)

采用VHDL语言实现基于ＢＭ算法的ＲＳ译码器，附件为整个工程文件，内附波形仿真图。程序在QUARTUS II 9.0下仿真通过

verilog alu 8bit for engineers

数字频率计 数字频率计-Digital frequency meter digital frequency meter

当年本科时的毕业设计，信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter

数字钟vhdl主要分为正常显示与报时功能(Digital clock vhdl)

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

通过神经网络实现的PID算法，整个工程文件，调试通过。(By PID algorithm neural networks, the entire project files, debugging through.)

SPI控制器，基于VERILOG描述，分模块设计，共6个模块，时钟产生模块，移位模块，主模块，从模块，定义模块，顶层模块。(SPI controller, based on the VERILOG description, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top module.)