展位乘数 VHDL 源代码

Toplevel VHDL Structural model of a system containing 8051 -Toplevel VHDL Structural model of a system containing 8051

Ethernet Media Access Controller

LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device

红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序(Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO)

基于altera公司MAX10型FPGA的ADC调试程序(ADC-based debugger altera company MAX 10 type of FPGA)

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)

FPGA设计的I2C总线控制器的MASTER端的程序-FPGA Design of I2C Bus Controller MASTER-side procedures

入门，verilog语言，实现字符型液晶1602的显示，及按键控制-verilog

Verilog编写的简单异步串口 完全原创，站长请查看内容-Verilog prepared by the simple asynchronous serial completely original, the station can be accessed content