四VHDL模块的家庭，已经过测试，在ISE8.1通过

这是一个瑞萨R78/G13的SPI演示程序，详细的放置了说明，很有用的源码(This is one of the SPI Renesas R78/G13 demonstration program, placed a detailed description of very useful source)

matlab 程序 伪随机码的捕获,我传的都是这方面的资料！(failed to translate)

自己编写的AD7667的数据采集程序，因为之前没用过，首次写！

异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation

用CPLD驱动数码管，实现从0000计到9999，数码管是用动态显示，程序用VERILOG完成的-CPLD drives with digital control, of from 0000 to 9999, digital control is a dynamic display, the program completed with VERILOG

Verilog代码，适合于初学者进行学习，是基于DE2平台的代码。(Verilog code, suitable for beginners to learn, is based on the DE2 platform code.)

卷积程序的Verilog程序，实现卷积功能(Convolution program Verilog program to achieve convolution function)

QC LDPC的编码译码 代码与论文配套 是研究生毕设 可运行 代码风格优秀(QC LDPC Coding and Decoding Code and Paper Matching are Excellent Style of Running Code for Graduate Students)

具有16个校验位的RS编码器，在FPGA上实现。(With 16 RS encoder, the parity bit in the FPGA.)

基于EDA的八音自动播放电子琴设计 内有VHDL语言设计 有-The octave-based EDA player automatically have a flower design language VHDL design