基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信

线性伸展TDC的verilog，包含门级网表(TDC linear stretch of verilog, includes gate-level netlist)

program in hdl that this open mind in digital resources

bch 编码和译码，用硬件语言vhdl实现(bch edcode and decoder)

说明：  基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)

program for half subtractor.

实现ITU-BT1120数字并行接口的编码和解码(decode and encode ITU-BT1120 parallel digital interface)

EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)

简单的8个CPU，包含PDF文件。他们可以查看详细信息

该文件用在CPLD上的，和C语言很接近，5位的计数器一个。-the documents on the CPLD, and the C language is close to that of the five counters one.

VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)