verilog code for counter four

高级verilog编程实现讲义，全英文讲义 -Senior verilog programming lecture notes, handouts in English

Quartus环境下的7段扫描显示电路的源程序(Quartus environment of the seven scanning display circuit of the source)

这是spi接口传输的一部分内容，本源码一共三部分，功能：spi接口的的实现即对外设的读写数据-This is the spi interface transfer part of the contents of a total of three parts of this source, function: spi interface that the realization of the read and write data to the peripheral

基于FPGA的图像压缩算法程序，自己写的，可以参考一下(FPGA-based image compression algorithm, write your own, you can refer to)

用vhdl语言编写的程序，可以播放乐曲，有分频模块，可播放梁祝等歌曲。

说明：  biss协议源码交流 verilog hdl源码，测试可用(Biss protocol ,achieved by verilog HDL,can be verify using modelsim or other simtools.)

Verilog HDL 写的SVPWM 算法的实现，使用的是altera 风暴系列的FPGA，占用资源1w+逻辑宏单元(Verilog HDL ，SVPWM)

利用数字电路知识，进行二十四小时计时，并有闹钟与蜂鸣器功能-Knowledge of the use of digital circuits, the 24 hours time, and there is an alarm clock function and buzzer

数字钟(Digital clock)

成功解决FPGA设计时序问题的三大点.word说明文档，很详细(FPGA design timing problems successfully solved the three points)