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A clock procedures, as well as stopwatch, I feel pretty good, there is a need to...

于 2022-03-12 发布文件大小:2.04 kB

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一个时钟程序，还有跑表，感觉相当不错的，有需要就下载吧-A clock procedures, as well as stopwatch, I feel pretty good, there is a need to download it

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说明： led blinking program.................

2012-01-12 18:05:09下载

积分：1
a program which divides the clock by 3
a program which divides the clock by 3

2022-01-25 14:21:33下载

积分：1
用VHDL语言实现的LDPC码的硬件语言实现，对比验证…
用VHDL语言编写的LDPC码硬件实现语言，相对于verilog的，比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple

2023-05-19 11:55:03下载

积分：1
ASYNC_FIFO_SYNTH
This file contains async fifo design

2014-03-01 20:48:22下载

积分：1
FPGA
基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop

2023-01-20 11:30:04下载

积分：1
SRAM 简单测试
SRAM简单测试，测试其性能及其速度，判断SRAM是否可用(Test its performance and speed to determine if SRAM is available)

2020-07-10 09:58:55下载

积分：1
关于FFT算法的FPGA实现（源码），数字信号处理不可少。
关于FFT算法的FPGA实现（源码），数字信号处理不可少。-FFT algorithm on the FPGA implementation (source code)

2022-02-26 14:45:28下载

积分：1
DCT_IDCT
H264/AVS中的离散余弦变换DCT以及反离散余弦变换IDCT的Verilog代码(H264/AVS the discrete cosine transform and inverse discrete cosine transform DCT IDCT of Verilog code)

2011-06-11 07:08:30下载

积分：1
Shift_reg
一个简单移位寄存器代码，verilog HDL编写(a simple shift register example，write with verilog HDL)

2012-03-26 21:36:01下载

积分：1
FPGASPI
FPGA SPI 主要模块全部涵盖时序解释与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

2020-12-09 13:49:20下载

积分：1

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A clock procedures, as well as stopwatch, I feel pretty good, there is a need to...

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