A clock procedures, as well as stopwatch, I feel pretty good, there is a need to...

uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps

FPGA控制外边led，并实现跑马灯等多种效果，用户可以自行控制(FPGA control outside led)

说明：  利用Matlab/simulink实现电力仿真，其中单相逆变可用于多电平变流器的基础使用，本案例提供了不同调制手段实现逆变的模型(Matlab / Simulink is used to realize power simulation, in which single-phase inverter can be used as the basis of multi-level converter. This case provides the inverter model with different modulation means)

生成一个M伪随机序列码，在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)

坦克游戏用VHDL语言编写。Altera的随身携带套件DE1。PS2键盘接口和VGA

PWM整流器的死区延迟的VHDL编程，可以参考一下(VHDL programming PWM Rectifier dead-band delays)

对视频编解码芯片ADV7181进行合理的配置，使其输出符合ITUR656标准的视频流-Of the ADV7181 video decoder chip for a reasonable configuration, so that the output in line with the standard video streaming ITUR656

VHDL Code For Full Adder By Data Flow Modelling

一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的PCI位码文件及配置程序。-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of the PCI code files and configuration procedures.

产生VGA彩条信号(Verilog 语言）-Generate VGA signal