A clock procedures, as well as stopwatch, I feel pretty good, there is a need to...

GPS信号结构,C/A码产生方式及其测距码研究(GPS signal structure and ranging code research)

这是一个最最常用的用vhdl写的状态机，几乎哪儿都用得到(a very good state machine)

串口收发程序，成功通过仿真，可以用来学习(Serial transceiver,It is successful through simulation and can be used to learn)

EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计(EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design)

上海交大关于基于FPGA的DSCDMA的实现的毕业设计(Shanghai Jiaotong University based the FPGA DSCDMA, achieve graduation design)

vhdl对dds的原理设计，由衷要得论文价值。不后悔-right dds VHDL design principle, we sincerely value of fine papers. No regrets

工程实用观点，简单介绍集成电路的传统设计语言现状。(Practical engineering point of view, the traditional integrated circuit design brief language status.)

verilog 或门程序 初学者必备。。。。。。。。。。。。(verilog )

VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL standard was revised in 1993, 2000, and 2002. In each revision, new language features were added and some existing features enhanced. The aim in each revision was to improve the language as a tool for design and verification of digital systems. Since the 2002 revision, there have two parallel efforts to further develop the language. The first was the VHDL Procedural Interface (VHPI) Task Force, a subcommittee of the IEEE P1076 Working Group. The VHPI Task Force prepared an interim amendment to the standard, formally approved by IEEE in March 2007. The amendment is titled IEEE 1076c, Standard VHDL Language Reference Manual―Amendment 1: Procedural Language Application Interface.

人的移动的跟踪，VERILOG实现，能跟踪人的画面移动(Tracking the movement of people, VERILOG realize that can track the person)