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这个代码是Verilog HDL。
this Code is in verilog HDL.
This Code is for piplined processor with 4 opcode.
this will work in three cycle latch, decode and exicute..
test bench for xilinx ise is laos given
- 2022-02-12 09:39:12下载
- 积分:1
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Basic-system-of-nexys3
the basic system of nexys3(soft core)
- 2012-09-21 23:41:14下载
- 积分:1
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一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (mo...
一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
- 2022-08-21 18:15:23下载
- 积分:1
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coverlater
本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码,能够成功地编译和仿真。(This procedure is in circumstances Quartus7.2 compile a simple (2,1,3) convolutional code, can successfully compile and simulation.)
- 2021-03-13 20:49:24下载
- 积分:1
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APB 总线
APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
- 2017-08-22 16:04:06下载
- 积分:1
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cordic_base_j
This code implement a interation in cordic pipelline
- 2014-10-30 01:47:24下载
- 积分:1
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ad0809
adc0809 转换,verilog代码(adc0809 conversion, verilog code)
- 2020-12-21 11:09:08下载
- 积分:1
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reader
实现verilog读写txt文件,从sut.txt从读取数据,进行操作后,写入out.txt(Realize verilog read and write txt file)
- 2020-11-15 21:29:41下载
- 积分:1
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WORK
运用VC编程的带LCD显示的信号发生器可用三个开个调节输出三个波形(Signal generator can be used three to open a regulator output waveform using VC programming with LCD display)
- 2013-03-02 16:13:27下载
- 积分:1
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rs-codec-8-16
RS[255,223]纠错码verilog源码,包含编码和解码模块,以及testbench等。(Verilog source code for RS[255,223] encoder and decoder, with testbench included.)
- 2021-04-28 15:58:44下载
- 积分:1