A clock procedures, as well as stopwatch, I feel pretty good, there is a need to...

串口收发程序，成功通过仿真，可以用来学习(Serial transceiver,It is successful through simulation and can be used to learn)

Altera DE2 开发板试验2 第1部分VHDL答案(Altera DE2 Lab2 part1 VHDL answer)

OFDM中的IFFF模块实现，基于verilog实现，通过验证(OFDM module in IFFF)

URAT 部分VHDL源码 大家多多支持 哈哈 -VHDL source URAT part of U.S. support of Haha

基于FPGA的VGA驱动代码VHDL 在显示屏显示一个汉字-FPGA-based VHDL code of the VGA driver that a character in the display

　M4A564/32 CPLD VHDLＡ程序，调试可用,51扩展.-M4A564/32 CPLD VHDLA procedures, debugging is available, 51 to expand.

ALTERA上DE2平台，利用内部50M Hz时钟，在数码管模拟显示时间(时分秒)。-ALTERA on DE2 platform, using internal 50M Hz clock, in the digital control simulation show time (hours minutes and seconds).

32-bit shifter, shifter, 32-bit.Very goog as a study file.

说明：  AXI4-Lite总线的主从机读写，例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)

ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)