fpga里实现 uart 经典 vhdl语言写的 ise工程文件

自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)

listing program clock

通过EMIF连接fpga与dsp的代码-Through the EMIF connection FPGA code with dsp

i have coding for verilogHDL and VHDL. so please i want know that coding..

四位动态刷新数码管显示，ＶＥＲＩＬＯＧ代码，含详细的中文注释．-Four dynamic refresh digital tube display, VERILOG code, with detailed notes in Chinese.

单片机4路ad模数转换数码管动态显示程序(4-way ad microcontroller analog to digital conversion digital tube dynamic display program)

二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)

基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考-FPGA-based high-performance 32-bit floating-point nuclear FFTIP development, engineering and technical personnel for reference fpga

直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.

数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)