杰姆斯阿姆斯壮的VHDL设计，源代码

利用FPGA控制VGA显示器显示字符汉字的程序，里面有注释。(VGA display with FPGA control procedures Kanji characters, there are comments.)

此VHDL语言程序可以控制液晶屏幕任意动画播放(The VHDL language program can control the LCD screen any animation)

说明：  等精度测频法，有需要的可以下载看看哟，word中包含的代码(Equal Precision Frequency Measurement Method)

圖形介面乘法器,也可自行使用verilog去改(Graphical interface multiplier, also free to use verilog go and change)

TLC5510的驱动程序，采用Verilog语言编写(TLC5510 driver, the use of Verilog language)

利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综合和时序仿真。-LMP

用verilog在FPGA内部实现8051内核，超好、超难找的资料！共享出来！(Verilog FPGA internal 8051 core, super, super hard to find! Shared out!)

数字跑表 该跑表具有启动、复位、暂停、暂停后继续计时等功能 能显示的秒计数时间精确到小数点后第二位，即能显示**.**s 按钮设置防抖-Digital stopwatch in the stopwatch with start, reset, suspend, suspended after the time and other functions can show the seconds counting time accurate to the second place after the decimal point, that can show**.** s Anti-Shake button settings

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.

此代码是SPI接口的Master的Verilog源代码，经上板测试是没有问题的，请大家放心使用 (This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use)