杰姆斯阿姆斯壮的VHDL设计，源代码

基于Verilog HDL的数字电压表的程序-Verilog HDL-based procedures for the digital voltmeter

说明：  中科院FPGA的课件！纯英文，比较简单，适合刚刚接触FPGA的小白！(Chinese Academy of Sciences FPGA courseware! Pure English, relatively simple, suitable for Xiaobai who just came into contact with FPGA!)

交织和解交织模块，采用矩阵交织方式，且有两套并行存储器，可以实现连续数据流操作，不会有数据滞留和丢失-Intertwined intertwined reconciliation module, interwoven matrix approach, and has two sets of parallel memory, you can realize continuous data stream operations, will not have data retention and loss

train controler by verilog

Conduct a digital system ( electronic lock ) using hierarchic methodology . An electronic lock is a device that allows access or opening of a system , as long as the key or combination to enter match with which it is predefined in said lock .

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a RAM memory.

Verilog 语言编写 PCI9054 控制器的接口电路，实现 PCI总线到本地 8 位总线的转接控制(The Verilog language writes the interface circuit of the PCI9054 controller to realize the transfer control of the PCI bus to the local 8 bit bus)

一种计算高阶矩阵奇异值分解的FPGA实现方法。(A high-end computing matrix singular value decomposition of the FPGA realization method.)

CPLD LATTICE1032测试模式代码-CPLD LATTICE1032 test model code

这是本人设计的一个关于VME总线接口的FGPA程序，FPGA一边连接ARM LPC2294，一边连接VME总线，FPGA采用的XILINX公司的SPARTANII系列，程序包包含完整的工程文件-This is my design of a VME bus interface on the FGPA procedures, FPGA side of the connection ARM LPC2294, while connecting VME bus, FPGA using the XILINX Inc. SPARTANII series, the package contains a complete project file