本设计可直接用作时钟计数器

UG586 - Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )(UG586- Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB ))

本文介绍了使用verilog语言进行硬件设计的一些基本技巧-This paper describes the use of Verilog hardware design language, the basic skills

NAND型闪存接口程序 里面包含了datasheet以及测试程序 (NAND flash memory interface program)

这是一个时钟的VHDL的源程序，里面包含有源程序，还有工程文件对大家很有帮助-This is a clock VHDL source code, which contains the source code, as well as engineering documents helpful to everyone

dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies

3g-sdi驱动器，用于全高清视频FPGA解决方案(3g-sdi driver)

FPGA做波形发生器，产生8种波形，包括三角波，正弦波，锯齿波，方波等。(FPGA is used as waveform generator,Generate 8 waveforms, including triangle, sine, sawtooth, square, etc.)

USB设备接口的驱动程序，采用verilogHDL语言编写，并包含相关说明资料(USB device driver interface, using verilogHDL language, and contains descriptive information)

msk比特误码率matlab仿真 匹配滤波器(the msk bit error rate matlab simulation matched filter)

GMSK调制基带眼图仿真源代码，基于MATLAB(GMSK modulation baseband eye diagram simulation source code, based on MATLAB)