design a module from a trip data flow channeling Lane detected bitstream "1...

利用VHDL语言和模块化设计实现PCM编译码的功能，整体工程和代码全有。(PCM encode and decode by VHDL in Quartus2. )

一些简单的VHDL实例，主要是介绍一些基本逻辑们及一些组合、时序电路的例子，供大家参考-Some simple examples of VHDL, mainly to introduce some basic logic and some combination of sequential circuit examples for your reference

说明：  ADV7179芯片的驱动程序，基于FPGA硬件实现，已经验证可以使用(ADV7179 chip drivers, FPGA-based hardware implementation has been verified using)

本代码实现了 ； ；CORDIC  ； 算法语言；

FPGA的测频程序，用了D触发器，能测1hz到几百hz(FPGA frequency measurement procedures, using a D flip-flop, can be measured to a few hundred hz 1hz)

PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF

VerilogHDL,对初学者很有帮助的,可以一下的!-VerilogHDL, very helpful for beginners, you can look in!

VHDL Language Reference courses part4

实现米粒状态机 用verilog语言实现状态机的过程(Implement a state machine with a grain of rice verilog state machine language course)

VHDL examples for counter design, use QuickLogic eclips