design a module from a trip data flow channeling Lane detected bitstream "1...

這裡提供Auto Gain Control 的詳細代碼與功能介紹(Here are details of the code and the Auto Gain Control Functions)

等精度测频法，有需要的可以下载看看哟，word中包含的代码(Equal Precision Frequency Measurement Method)

FSK/MSK/GFSK/GMSK DIGITAL DEMODULATOR VHDL SOURCE CODE OVERVIEW

Rotary Encoder Reading the Rotary Encoder and indicating the selection through a LED placed on the front panel. Events counter for the Rotary Encoder and displaying the events on the front panel Project: events counter for the rotary encoder and displaying the events on the SSD Pmod (Seven-Segments Display Programable module).

一个高级培训班的内部资料,非常宝贵,读者可以掌握FPGA的基本思路-A high-level training of internal information, are very valuable, readers can grasp the basic ideas FPGA

verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)

SHIFT_8REG是8位的一个具有移位功能的寄存器，每一次数据打入都会从这个寄存器的最低位打入，并相应进行向左移位。 ODD_110BREG是一个3位的备份寄存器，寄存器中存放的是奇数帧的同步头，也就是110。 EVEN_9BHREG是一个8位的备份寄存器，寄存器中存放的是偶数帧的同步头，也就是10011011。这两个寄存器的初始值在系统一开始就打入。 -SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register is stored in the odd frame synchronization head, is 110. EVEN_9BHREG 8 is a backup Register, which register is kept even the first frame synchronization, is 10011011. This register the two initial value of the system into a start.

Circular_Buffer，流水线型多位缓存器，verilog语言描述。通过modelsim 6。0仿真，quartus 综合通过。-Circular_Buffer, type a number of buffer lines, verilog language description. Through modelsim 6. 0 simulation, quartus integrated through.

vhdl实现vga接口设计，非常实用的一段代码，学习用-vhdl achieve vga interface design

彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)