degilent atlys board ucf

有用的数字钟设计文档，有秒表、闹钟等模块，希望对大家有用！(JUST LEARN FROM IT!!ENJOY!)

用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。-VHDL language using FPGA-based waveform generator. Does the need for experimental waveforms generated very useful.

硬件设计VHDL学习100例(站长推荐)-VHDL hardware design study of 100 cases (chief recommended)

Verilog_HDL源码， Verilog_HDL源码-Verilog_HDL source, Verilog_HDL FO

800 x 480 / inch lcd

用VHDL语言编写的LDPC码硬件实现语言，相对于verilog的，比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple

本程序调试了TI的高精度模数转换芯片ADS1115,此模数转换器采用双积分型，16位，为IIC通信方式，调试较复杂，在对直流采集方面有着广泛的应用(This program debugging TI s high-precision analog-digital conversion chip ADS1115)

说明：  模拟交通灯 verilog CPLD EPM1270 源代码(Simulation of traffic lights verilog CPLDEPM1270 source code)

这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核，文档齐全-this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation

在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imitate reality, taxi billing.