degilent atlys board ucf

Verilog写的 8 位超前进位加法器-Verilog write 8-bit CLA

说明：  高清电子书4本合集-Verilog HDL数字系统设计教程4本合集(Digital circuit design Verilog HDL digital system design)

USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code

用Verilog实现的 哈佛结构的简单指令集CPU程序，由ALU、地址译码器、指令译码器等部分组成(Part of a simple instruction Verilog realize the Harvard architecture CPU program set by the ALU, address decoder, an instruction decoder, etc.)

MBD-FPGA数字滤波器设计基本流程,基于DSP builder(MBD-FPGA basic process of digital filter design)

RTL8369开发资料，包括手册，图纸，Layout说明等等(RTL8369 development information, including manuals, drawings, Layout Guide.)

基于FPGA的波束形成，包括ad转换，数据存储等部分。。(FPGA-based beamforming, including ad conversion, data storage and other parts. .)

用verilog hdl编写的一些例程，包括加法器/减法器等等，例子较多就不一一列举了(Verilog hdl prepared with some routines, including the adder/subtraction, etc., for example, more is not to enumerate the)

vga很好的学习材料，测试程序，欢迎下载(vga good learning materials, testing procedures, please download)

4位2选1多路选择器的设计与实现。nexy3开发板。本实验中用Verilog语句来描述。(Xilinx ISE 12.3.nexy3.)