degilent atlys board ucf

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.(FPGA optical encoder input module, there is no experimental, but simulation technology, hope to have reference value.)

verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)

mc8051内核,VHDL程序,内有说明,超详细.-mc8051 kernel, VHDL program, which has made it clear, super-detailed.

VERILOG实现无分频时钟，包括测试文件，经过验证可用(VERILOG is no difference between the frequency of the clock implementation, including test papers, can be used after authentication)

一个完整的viterbi译码程序和测试的程序-A complete viterbi decoding procedures and test procedures

URAT 部分VHDL源码 大家多多支持 哈哈 -VHDL source URAT part of U.S. support of Haha

本例为DAC0832接口电路VHDL原代码-The DAC0832 Interface Circuit Example for VHDL source code

在altera DE2 的开发板上采集图像，到lcd显示的原程序 。-In altera DE2 development board collecting images, lcd display to the original procedure.

ISE Design Suite Software Manuals and Help - PDF Collection,ISE 软件手册以及帮助。(ISE Design Suite Software Manuals and Help- PDF Collection, ISE software manuals as well as help.)

介绍了基于VHDL的可编程分频器在波形发生器中的应用的方法，利用这一方法， 可使波形频率在大范围内变化。()