LDPC码的编码和解码过程。有testbentch。

vhdl测试程序，用于初雪者熟悉hdl的具体语法应用。比较简单了。(VHDL test procedure for the First Snow hdl who are familiar with the application of specific syntax. A relatively simple.)

ppm调制的verilog代码 可实现ppm调制(ppm modulation verilog code ppm modulation)

扰码器的verilog实现,参考802.11a相关标准(Scrambler in verilog implementation)

利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter

flii adder wave form 3

基于FPGA设计的经典打砖块小游戏。游戏简单易玩。(FPGA design based on the classic Arkanoid game. Game easy to play.)

异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been

说明：  Xilinx ISE License集合，包含Vivado、ise的破解license，安装ISE后loading license即可完成，最全的器件库(Xilinx ise license Collection, including Vivado and ISE cracking licenses. After ISE is installed, the loading license can be completed, which is the most complete device library.)

基于Verilog HDL的通信系统设计(Design of communication system based on Verilog HDL)

it contains pdf file which has vhdl program of uart (universal asynchoronus receiver and transmitter). which very simple and easy to understand