LDPC码的编码和解码过程。有testbentch。

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE

该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序，FPGA上的VERILOG通信程序。(The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, including PC, the USB firmware, drivers, FPGA' s Communication Program)

应用背景用键盘上的应用程序，如文字，以矩阵为主导。关键技术键盘的PS / 2在DE2 115编程。它是有用的，重要的是要了解如何在DE2用VHDL键盘程序

数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证-VHDL design of digital stopwatch, accurate to the percentage of seconds in the six digital tube display, respectively, have seconds, minutes, hours, through the target chips EPF10KLC84-4 verification

熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)

verilog描述的基于LMS的自适应噪声消除器ANC算法。用于数字音频处理。(The verilog Description LMS-based adaptive noise canceller ANC algorithm. For digital audio processing.)

基于BASYS开发板的波形发生器和示波器设计，可以在显示器上显示波形，共有三角波方波锯齿波正弦波四种

hdmi 视频编解码输入输出模块，verilog实现(hdmi encoder and decoder in verilog.)

basic verilog code on siso, piso, sipo

使用Ｖeriolog hdl 编写手机屏测试程序．-Veriolog hdl prepared to use cell phone screen test.