实现了简单的电子表功能，是24小时，用VHDL所编写的，quartus ii 7.2...

实现了从摄像头读取数据到液晶的显示，利用了cycloneV 和康欣的开发板资源(It realizes the display of reading data from camera to liquid crystal.)

曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code

文档主要是关于TFT-LCD的相关资料，是有关TFT-lcd芯片的结构与设计理念，对于在这方面学习的朋友有比较大帮助(402 output thinfilm transistorliqu idcrystal display(TFT-LCDdriver integrated circui(ICwith power controlbasedon the number of color stobe displaye disdescribed. Toachievethistypeofpowercontrol,referencevoltagebuffersare turnedonandoffaccordingtotheselectednumberofcolors.)

---实现的部分VHDL 程序如下。 　　--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if(--- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no))

verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System

cordic算法的fpga的实现 采用altera芯片-cordic realization algorithm using fpga chip altera

4 bit ROM for Quartus

说明：  PID算法用verilog语言实现，实测可用，由三个模块组成(The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.)

与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。(I2C-Master Core)