实现了简单的电子表功能，是24小时，用VHDL所编写的，quartus ii 7.2...

An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.

运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)

基于FPGA的画中画处理PDF技术文档，采用SD卡里图片读出来做为底图，然后再图上叠加另外一个图片或者视频(Based on the FPGA picture in picture processing PDF technical documentation )

很有用的10bit串并转换verilog程序，需要的可以拿去参考下，在quartusII上已验证过(Useful 10bit string and convert verilog program, need to take a reference, has been verified in quartusII)

ethernet 10 0M MAC-ethernet MAC 10,100 M

adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)

files describe how to configure an ADV7180

Use full for knowing board details while making projects on FPGA and matlab simulations

DS18b20 temperature sensor vhdl code

说明：  用VERILOG语言实现的频谱分析仪（FFT)(VERILOG language with the Spectrum Analyzer (FFT))