Altera company s FPGA using VHDL to the development, use quartus2 9.0 software E...

FPGA 点亮数码管的灯，本例程支持6位数码管，因为我的FPGA开发板是这样子的(The lamp of digital tube illuminated by FPGA)

基于Verilog的图像采集、处理和存储程序，初学者参考，高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)

利用Quartus 综合简单的计时器功能，欢迎大家下载、参考。谢谢大家的支持！

Traffice LED Controller base on FSM 1. for crossroad, each road with 3 led: green, red, yellow. 2. only use one counter.

5604FPGA驱动，能显示数字（5604里面为4个595）(5604 FPGA driver, able to display digital (5604 contains 4 595))

描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.

资源描述这个包提供了一个UDP／IP核心架构的一个开源的VHDL实现和PC机与FPGA接口传输基础C类型（字符、16 / 32 / 64位的整数，浮点数和双打）。

关于LDPC解码的verilog程序，包含设计代码和验证环境(LDPC decoding on verilog procedures, including the design code and verification environment)

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)

veilog 代码 用户可以直接调用，作为底层模块。同时已经编译成功，可以作为基本单元库。-veilog code user can derict use it for the base mode.