This code that genetes a square, sawtooth and a triangular waveform. It is usefu...

基于CPLD芯片EPM570的verilog hdl串口程序(the UART verilog hdl code based on CPLD chip-- EPM570)

说明：  本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)

基于用户自定义模块的实时时钟的设计；Qsys硬件设计；(Custom real-time clock module-based design Qsys hardware design )

自己写的FPGA实现电子琴的VHDL程序，曲目是两只老虎，用到一些模块，和片内存储间，呵呵(FPGA realization of his keyboard to write the VHDL program, tracks are two tigers, a number of modules used, and on-chip storage room, huh, huh)

FPGA读取LM75A温度数据，并在段码LED上实时显示。(The temperature data of LM75A are read by FPGA and displayed on segment code LED in real time)

High-Speed Data Serialization and Deserialization(840 Mb/s LVDS) for xilinx fpga

HDLC接口协议的FPGA实现使用verilog-design of HDLC

说明：  LVDS De-serialization

该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间(The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain)

用verilog hdl语言编写的fpga与片外sram 的读写控制(With the verilog hdl language fpga sram chip with read and write control)