线阵CCD时序驱动

WCDMA数字直放站中数字预失真研究及其FPGA实现(WCDMA Digital Repeater digital pre-distortion and its FPGA implementation)

最大最小值寻找程序，可以实现自动查找最大值与最小值(min_max_finder)

lvds transmitter megafunction (lvds transmitter megafunction)

10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed using less than 2000 LCs/LEs to implement full function. It will use inferred PADs to reduce technology dependancies. The whole project will be finished in TEN weeks inluding verilog coding,RTL level verification. A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.

基于NiosII 的SOC FPGA验证系统，适用初学者学习Altra Quartus II软件，以及C语言 veriog，以及MCU调试流程

说明：  是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)

VHDL code of a counter Code VHDL d un compteur

定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)

ZEDBOARD的管脚分配图和约束文件，包括PCB图和xdc文件(Pin assignment of ZEDBOARD)

turbo product code used in error correction