四位全加器的Verilog源代码

I2C IP for Quartus V9.0 sp2, can used in SOPC builder.

Quartus环境下使用Verilog编写的HDB3编解码程序，RTL和时序仿真已过(Quartus under the environment of a HDB3 protocol procedures written in Verilog, RTL and timing simulation has be passed)

I2C verilog源代码实例并带有验证平台(iic source code and testbench)

精简指令集的整体设计 实现了简单的8位RISC CPU的基础功能，包括加，减，与，或，异或等操作，还可以对RAM进行读取或写入操作。另外，还有RISC_CPU的实验报告，里面包含了RISC-CPU的设计原理及仿真结果。

一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加(A 32-bit floating-point adder can be both within the IEEE 754 format to add value)

一种基于CPRI标准的WCDMA NoddeB射频光纤拉远接口FPGA设计.pdf (CPRI compliant the WCDMA NoddeB RF fiber pull far from the interface of the FPGA design. Pdf)

：采用FPGA来实现一个基于OFDM技术的通信系统中的基带数据处理部分，即调制解调器。其中发射部分的调制器包括：信道编码（Reed-Solomon编码），交织，星座映射，FFT和插入循环前缀等模块。我另外制作了相应的解调器，可以实现上述功能的逆变换。(: Using FPGA to implement a technology-based OFDM communication systems in base-band data processing part of the modem. One part of the modulator launch include: channel coding (Reed-Solomon coding), interleaving, constellation mapping, FFT and cyclic prefix insertion modules. I also produced a corresponding demodulator can achieve the above-mentioned inverse transform function.)

基于verilog的出租车付费系统 带验证模块

vhdl 实现fpga 闪灯控制 流水线闪灯 还用signalTAP进行检测，给初学者参考(vhdl fpga flash control lines to achieve flash is also used signalTAP testing, to advanced users)

1024点fft verilog hdl(1024-point fft verilog hdl)