四位全加器的Verilog源代码

1、PC和寄存器组使用时钟触发。 2、指令存储器和数据存储器存储单元宽度一律使用8位，即一个字节的存储单位。 3、控制器部分可以考虑用控制信号真值表方法（有共性部分）与用case语句方法逐个产生各指令其它控制信号相配合，注意：信号必须与状态配合。。当然，还可以用其它方法，自己考虑。 4、试用的汇编程序，而且必须包含所要求的所有指令。Slt、sltu指令必须检查两种情况：“小于”和“大于等于”；beq、bne指令必须检查两种情况：“等”和“不等”。这段汇编程序必须尽量优化，同时，给出每条指令在内存中的地址。(1, PC and register groups are clocked. 2, the command memory and data memory storage unit width will use 8 bits, that is, a byte storage unit. 3, the controller part can be considered with the control signal truth table method (common part) and with the case statement method to produce each command other control signal match, Note: the signal must be with the state. The Of course, you can also use other methods to consider their own. 4, try the assembler, and must contain all the required instructions. Slt, sltu instruction must check two cases: "less than" and "greater than or equal to"; beq, bne instruction must check two cases: "wait" and "unequal". This assembler must be optimized as much as possible, giving the address of each instruction in memory.)

FPGA按键加蜂鸣器实验： 加延时防抖+蜂鸣器(Experiments of keys and buzzers in FPGA)

A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.

说明：  串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。(source code, the code used veilog HDL language, and after I repeatedly verified.)

说明：  基于sv的uvm平台搭建实战，对于验证方法学来说，分层的测试平台是一个关键的概念。虽然分层似乎会使测试平台变得更复杂，但它能够把代码分而治之，有助于减轻工作负担，而且重复利用效率提升。验证平台可以类似分为五个层次：信号层、命令层、功能层、场景层和测试层。(Construction of UVM platform based on SV)

Complex of three-point Gauss-lengend the Formula pi, Including orbital maneuvering simulation, initial orbit calculation, University of numerical analysis algorithms.

The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).

FPGA连接PCI9504的电路图。以及PCB文件(FPGA connected to the circuit diagram of the PCI9504. And PCB files)

半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

通过matlab代码对一组输入的字符串进行编码后，通过matlab内置函数对进行编码后的字符串进行哈夫曼树绘制。 通过matlab代码对一组输入的字符串进行编码后，通过matlab内置函数对进行编码后的字符串进行哈夫曼树绘制。