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7x7块交织器的FPGA设计
基于FPGA的7x7块交织器设计,程序分交织、解交织两部分,并在QUARTUS II 9.0 下仿真通过,内附模块详细端口说明及仿真分析文件。
- 2022-12-16 23:40:03下载
- 积分:1
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CRC_restored
mpeg-2 crcr32计算的代码,采用verilog编写,验证通过(mpeg-2 crcr32 caculate)
- 2011-09-25 10:54:08下载
- 积分:1
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jtag
verilog jtag源码及原理,还有debug模块。边界扫描等(verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.)
- 2021-04-27 14:18:44下载
- 积分:1
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该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块...
该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块-the source for several sine ROM, has been compiled and passed, can be directly downloaded, not internal ROM containing sine table, the Acer ROM module
- 2022-02-15 13:48:53下载
- 积分:1
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dpll
数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法(Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis and computer simulation of specific methods)
- 2017-04-04 23:13:28下载
- 积分:1
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VHDL实例应用的经典,大家学习必看的书籍。
VHDL实例应用的经典,大家学习必看的书籍。-VHDL classic example of the application, see U.S. study books.
- 2023-04-30 04:00:04下载
- 积分:1
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基于FPGA的DDS
基于FPGA的DDS。可以产生三种波形:正弦,方波,三角波。频率分辨率0.012Hz。频率从0至25MHz任意可调。(FPGA-based DDS. Can produce three waveforms: sine, square, triangle wave. Frequency resolution 0.012Hz. Frequency is adjustable from 0 to 25MHz.)
- 2013-08-05 07:06:22下载
- 积分:1
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一个模拟视频输入转VGA视频输出的Verilog程序,视频解码芯片采用ADV7181B,VGA DAC采用ADV7123,强力推荐...
一个模拟视频输入转VGA视频输出的Verilog程序,视频解码芯片采用ADV7181B,VGA DAC采用ADV7123,强力推荐-an analog video input to VGA video output Verilog procedures, Video decoder chip used ADV7181B, VGA DAC used ADV7123, strongly recommended!
- 2022-03-07 12:48:23下载
- 积分:1
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inv_matrix
矩阵求逆模块硬件实现,用verilog语言,基于ISE开发环境(implement of inverse matrix)
- 2021-03-24 10:19:14下载
- 积分:1
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pll
说明: fpga配置锁相环完整程序,使用quartus IP核,Verilog语言。(FPGA configuration PLL complete program, Verilog language.)
- 2020-06-20 17:00:01下载
- 积分:1