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raised-cosine-filter
代码实现了一个根升余弦成型滤波器,2PAM信号通过此成型滤波器,并且匹配接收,画出了发送和接收波形,验证了代码的正确性。(The code designs a root raised cosine filter,2PAM signal transmitted through the filter and matched using the same filter, I plot the transmitted signal and received signal to verify the correctness of the code.)
- 2012-11-09 21:59:53下载
- 积分:1
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top
脉冲多普勒雷达回波信号相干积累的VHDL源程序(pulse Doppler radar echo signal coherent accumulation of VHDL source)
- 2021-04-22 20:28:48下载
- 积分:1
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用FPGA控制1602型液晶显示,显示一行英文语句。
用FPGA控制1602型液晶显示,显示一行英文语句。-show
- 2022-08-13 01:34:34下载
- 积分:1
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ad5791
在Quartus环境下编写,使用Cyclong系列芯片,配置七通道高精度AD5791,该例子为AD5791的FPGA配置使能代码,包括模拟数据输入模块,复位模块,命令接收是能配置模块。(AD5781,Digital signal convert to Analog signal)
- 2021-04-20 14:28:50下载
- 积分:1
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huxideng
用Verilog实现的呼吸灯,用Verilog实现的呼吸灯(Verilog huxideng)
- 2016-01-15 17:34:12下载
- 积分:1
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Verilog_HDL源码, Verilog_HDL源码
Verilog_HDL源码, Verilog_HDL源码-Verilog_HDL source, Verilog_HDL FO
- 2022-06-21 00:23:39下载
- 积分:1
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Altera FPGA IP core of the source code for the use of Altera FPGA design to prov...
ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
- 2022-04-30 06:15:53下载
- 积分:1
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用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。...
用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.
- 2022-02-25 16:18:57下载
- 积分:1
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基于FPGA的调制,实现了QPSK调制,所用芯片为Artera的CycloneIIEp2C5T114C8...
基于FPGA的调制,实现了QPSK调制,所用芯片为Artera的CycloneIIEp2C5T114C8-FPGA-based modulation, realize the QPSK modulation, the chip used for Artera
- 2022-06-16 16:50:45下载
- 积分:1
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multiply
由verilog编写的乘法器,通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。(Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.)
- 2008-12-30 20:51:33下载
- 积分:1