Calculation of square roots via ASM

verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)

说明：  实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

DDS in our camera design

几大代工厂的flash verilog源代码(flash verilog code)

VHDL写的串口，很好用，程序非常简单，可以调试用-Written in VHDL serial, very good, and the procedure is very simple, you can debug with

verilog ADPLL file with testbench

键盘接口电路的一个工程---包括vhdl源程序和编译后产生的相关文件-Keyboard interface circuit of a project--- including VHDL source code and compile the relevant documents after

spartan3e led fpga labview 8.6

程序设置了fpga 的 5x5点阵驱动程序，代码相对比较简洁，这个程序可以作为fpga输出控制，驱动稳压芯片工作，进而点灯