Calculation of square roots via ASM

Huffman encoder decoder verilog

数字逻辑课程设计，用vhdl实现红外线传输系统的课程设计，下载验证通过-Digital logic course design, using vhdl infrared transmission system to achieve curriculum design, download verified by

说明：  使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

说明：  用verilog编写的LVDS接口驱动程序，采用IOSERDES技术实现，经过Spartan6 FPGA调试验证，有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)

the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit "s multiplication.

里面包含了三段代码，主要是用matlab产生高斯随机信号以及高斯白噪声和色噪声，然后计算其数字特征及对这些信号进行频谱分析和功率谱分析，里面还有关于低通滤波器的设计的简单说明(Which contains three sections of code using matlab Gaussian random signals and white Gaussian noise and color noise, and then to calculate the numerical characteristics and spectral analysis and power spectral analysis of these signals, there is also the low-pass filter design BRIEF DESCRIPTION OF)

this example exchanges the NRZ code to the MANCHESTER code with moore output

74hc595 driver 8 led

可以给VHDL初学者看的实例，全部经过验证(VHDL beginners can see examples of all the proven)

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.