3-8译码器实验

设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter

Vivado同步计数器VHDL设计 具有异步复位和同步预置数功能 同步计数器同步计数器同步计数器(The Vivado synchronous counter VHDL is designed with asynchronous reset and synchronous preset function, synchronous counter, synchronous counter and synchronous counter.)

基于Basys3的数字钟实例，主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL(Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL)

用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)

VHDL语言基本数学运算库-VHDL basic arithmetic library

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)

简易信号波形发生器，可以产生四种波形，频率1k-20K步进可调。学习Verilog HDL的好例子。(imple signal waveform generator, can produce four waveform, frequency 1 k-20 k step can be adjusted. Learning Verilog good example of HDL. )

此程序基于ADC0809,它是CMOS的8位A/D转换器，片内有8路模拟开关，可控制8个模拟量中的一个进入转换器中。-Connection between ADC 0809, it was the eight CMOS A/D converters. Tablets containing eight analog switches, control eight of analog converters enter a Chinese.

《Verilog HDL 程序设计教程》2-"Verilog HDL Design Guide," 2