3-8译码器实验

通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)

基于有限状态机的健壮性测试研究。 关键词：健壮性测试；增强有限状态机；全球平台；安全通道协议(The Research of Robustness Testing Based on FSM)

VHDL入门级好教材《VHDL开发精解与实例剖析》(VHDL development solution with fine examples of analysis)

实现QR_RLS算法,基于fpga 的非线性功放的dpd实现(realize QR_RLS)

使用ALTERA的FPGA控制SDRAM的verilog程序(Use ALTERA s FPGA to control SDRAM s verilog program)

说明：  This is code of UVM CALLBACK function.

一个简单的FM调制模块，FM发射，用Verilog编写，基于Xilinx SPARTAN6 XC6LX9开发(A simple FM modulation modules for FM transmitter, using Verilog prepared, based on XILINX SPARTAN6 XC6LX9 Development)

实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.

说明：  利用vhdl语言编写的译码器程序，采用两种不同方式(The use of language decoder vhdl program, using two different ways)

The xapp851.zip archive includes the following subdirectories. The specific contents of each subdirectory below:   tl   - HDL design files   sim   - simulation files   synth - Synthesis related files   par   - Place/Route related files 以及DDR SDRAM控制器设置.pdf文件