基于VHDL语言的循环码编码器的程序，以一个（15，6）循环码为例...

FPGA设计中的时序分析及异步设计注意事项 (FPGA design timing analysis and design considerations for asynchronous)

这是用VHDL实现的8位加法器，对新手有点帮助。-This is achieved using VHDL adder 8, a little help to novices.

VHDL handbook is very nice and suitable guide to HVDL language

单口RAM带CLR信号的verilog程序。很详细的.(Single-port RAM with a CLR signal)

FIR带通、带阻滤波器设计，需要输入截止频率以及容许偏差。(FIR band pass and band stop filter design)

VHDL code of a counter Code VHDL d un compteur

GPS信号结构,C/A码产生方式及其测距码研究(GPS signal structure and ranging code research)

基于FPGA的DM9000A芯片的网络数据采集系统，基于NIOS架构，c语言编程，资料齐全，包含不止5个源程序，绝对受用！(FPGA-based the DM9000A chip network data acquisition system based on NIOS architecture, c programming language, the information is complete, contains more than 5 source code is absolutely good enough!)

说明：  OFDM的简易verilog仿真程序，环境是quartus，版本需要7.2以上(OFDM Modulation and Demodulation using Verilog in Quartus)

用VHDL实现视频控制程序(实现对图像的采集和压缩)-Using VHDL video control procedures (the achievement of the image acquisition and compression)