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pl_read_write_ps_ddr
说明: PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重,常常需要将 PL 端的大量数据实时送到 PS 端处理,或者将 PS 端处理结果实时送到 PL 端处理,但是各种协议非常麻烦,灵活性也比较差,直接通过 AXI 总线来读写 PS 端 ddr 的数据,这里面涉及到 AXI4 协议,vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
- 2021-01-22 17:46:44下载
- 积分:1
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JTAG
边界扫描技术相关资料,含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)
- 2016-02-24 19:10:03下载
- 积分:1
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ldpc
低密度校验码 ,很好用的代码,功能已经实现编码和译码(fpga ldpc)
- 2014-04-09 10:24:51下载
- 积分:1
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This application note explains the process of eveloping and debugging a hardware...
This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.-This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.
- 2022-01-23 11:16:04下载
- 积分:1
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FPGA_Timing_Constraints_byCamp
简要地说明时序约束的内容,对入门级的朋友相当起到引导的作用(Briefly describes the content of timing constraints on entry-level friends rather play a guiding role)
- 2013-10-30 23:20:53下载
- 积分:1
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VHDL language learning paradigm, the FSK
学习VHDL语言的范例,有关FSK-VHDL language learning paradigm, the FSK
- 2023-06-01 13:25:03下载
- 积分:1
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frequency divider
FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)
- 2019-04-27 23:35:12下载
- 积分:1
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shift_registers
Universal Shift Register
- 2009-06-12 17:29:13下载
- 积分:1
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FPGA_PSK
说明: 可以实现2PSK的信号调制,已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)
- 2019-05-09 16:29:17下载
- 积分:1
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program vending machine at the core function, with three kinds of commodity pric...
程序实现自动售货机的核心功能,设有3种价格的商品,可选择数量,有找钱功能。-program vending machine at the core function, with three kinds of commodity prices, the number of choice, having to function.
- 2022-12-29 09:45:03下载
- 积分:1