HDL的例子源代码2 / 5

以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)

用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.

基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信-Based on nios ii controlled altera de1 Development Board iic bus for communication with the at24c02

几个fpga竞赛的设计例-Several Example FPGA design contest

quartusII的环境下的基于Ep3C10144的KeyBoard程序-quartesII of the environment based on the KeyBoard program Ep3C10144

reversible Data Hiding in Encrypted Images by Reserving Room Before Encryption

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4X4电子密码锁的中央控制系统。控制6位输入。-4x4 electronic locks central control system. Six input control.

ENDAT 协议说明，包括时序等详细的说明，(endat Encoder characteristics)

华为内部资料，包括verilog电路设计，硬件工程师手册，verilog约束，synplify使用指南等。内容较全面。(Huawei internal information, including verilog circuit design, hardware engineers manual, verilog constraints, synplify use guides. Content more comprehensive.)