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matlab2DPSK
蒙特卡洛仿真图
这个程序对2psk信号进行仿真
前提是把信号能量归一化了
(This programme intend to realize the simulation of 2DPSK through MonteCarlo experiment.
intends
)
- 2013-05-04 13:18:00下载
- 积分:1
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可编程逻辑器件实验
运用VHDL语言编写的检测1111的序列检测代码和加法器,运用verlog语言的交通灯,流水灯,出租车自动计费器等
- 2022-07-17 23:42:22下载
- 积分:1
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ALTERA Cyclone1C20 Nios开发板,protel99格式
ALTERA Cyclone1C20 Nios开发板,protel99格式-ALTERA Cyclone1C20 Nios,protel99
- 2022-01-23 10:08:20下载
- 积分:1
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Electronic organ program design implementation and simulation of vhdl source cod...
电子琴程序设计与仿真的vhdl实现的源代码-Electronic organ program design implementation and simulation of vhdl source code
- 2022-02-02 22:03:59下载
- 积分:1
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myAdc9248
CycloneIV控制采样芯片AD9248-20MHz,VHDL语言(CycloneIV control sampling chip AD9248-20MHz, VHDL language)
- 2017-01-31 21:55:26下载
- 积分:1
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用vhdl写实用96例子
用vhdl写实用96例子, 有RAM,PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)
- 2017-09-13 14:55:39下载
- 积分:1
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proj-ASC
simple microprocessor that gives the greatest common divisor of 2 (4bit) numbers
- 2014-11-05 06:32:53下载
- 积分:1
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Xilinx FPGA moving data across asynchronous clock boundaries
Xilinx FPGA moving data across asynchronous clock boundaries
- 2022-03-05 12:30:25下载
- 积分:1
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chengxu_jieshou
nrf24l01发送代码,verilog实现NRF24L01通信(NRF24L01 send code, Verilog to achieve NRF24L01 communication)
- 2017-08-09 19:04:16下载
- 积分:1
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AXI-HP-ZYNQ
用Vivado IPI搭建的Zynq-7000 PS到PL通信过程,使用了AXI-HP接口,利用AXI-DMA IP实现直接读写DDR的过程,软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)
- 2020-12-01 20:39:27下载
- 积分:1