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wbm
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.(algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.)
- 2006-07-12 14:49:35下载
- 积分:1
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Some files
this is a sum for 2 digit numbers
- 2018-01-24 03:30:30下载
- 积分:1
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hgb_pci_host
说明: 内有一PCI 主 和PCI从,PCI TARGET 都是公开代码的,是工程文件,有仿真工程,使用说明。觉得好的就推荐一下。
本PCI_HOST目前支持:
1、 对目标PCI_T进行配置;
2、 对目标进行单周期读写;
3、 可以工作在33MHZ和66MHZ
4、 支持目标跟不上时插入最长10时钟的等待。
ALTERA的PCI竟然收费的!!!软件里面调试仿真了半天,终于调通了,到了下载就突然弹出窗口说包含了有限制的IP CORE,是限制使用的(There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of)
- 2008-09-16 18:57:25下载
- 积分:1
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FPGA
说明: 基于FPGA的数字式相位测量仪的设计与制作(FPGA-Based Digital Phase Meter Design and Production)
- 2010-04-16 19:40:41下载
- 积分:1
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AD7606URAT
Verilog实现高速AD7606数据采样,8通道,采样频率可调,支持串口数据发送,亲测可用。(Verilog AD7606 high-speed data sampling, 8-channel, the sampling frequency is adjustable, support for serial data transmission, pro-test is available.)
- 2021-04-16 21:38:53下载
- 积分:1
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digital_tsmc018
180nm数字教学库,内含各种标准数字单元(180nm digital lib for education, including standard cells)
- 2020-12-14 14:49:14下载
- 积分:1
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verilog基础练习,介绍怎样编写测试文件和仿真
verilog基础练习,介绍怎样编写测试文件和仿真-Verilog based on exercises, how to introduce the preparation of test documentation and simulation
- 2022-01-28 18:39:08下载
- 积分:1
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agc
数字自动增益控制 AGC (automatic gain control) Verilog(automatic gain control Verilog)
- 2021-03-11 19:29:25下载
- 积分:1
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串uart的vhdl,verilog,lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Veri...
串uart的vhdl,verilog,lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar
- 2022-04-12 23:45:53下载
- 积分:1
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dianzhen(ok)
驱动8*8点阵块显示汉字,可以自己根据要显示的内容随意更改,已通过验证。(Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.)
- 2010-12-28 16:42:07下载
- 积分:1